Directly write to gx fifo from dma

Grarak · Jan 24, 2025 · 8ad1aef · 8ad1aef
1 parent 45d55f1
commit 8ad1aef
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Showing 2 changed files with 29 additions and 11 deletions.
diff --git a/src/core/graphics/gpu_3d/registers_3d.rs b/src/core/graphics/gpu_3d/registers_3d.rs
@@ -286,7 +286,7 @@ struct Entry {
 
 impl Entry {
     fn new(cmd: u8, param: u32) -> Self {
-        Self::new_with_len(cmd, FIFO_PARAM_COUNTS[cmd as usize - 0x10], param)
+        Self::new_with_len(cmd, unsafe { *FIFO_PARAM_COUNTS.get_unchecked(cmd as usize - 0x10) }, param)
     }
 
     fn new_with_len(cmd: u8, param_len: u8, param: u32) -> Self {
@@ -1322,6 +1322,7 @@ impl Gpu3DRegisters {
         self.cmd_fifo.push_back(entry);
     }
 
+    #[inline(never)]
     fn post_queue_entry(&mut self, emu: &mut Emu) {
         self.gx_stat.set_geometry_busy(!self.cmd_fifo.is_empty());
 
@@ -1364,13 +1365,13 @@ impl Gpu3DRegisters {
         self.vec_result[index] as u16
     }
 
-    pub fn set_gx_fifo(&mut self, mask: u32, value: u32, emu: &mut Emu) {
+    fn queue_packed_value(&mut self, value: u32) {
         if self.gx_fifo == 0 {
-            self.gx_fifo = value & mask;
+            self.gx_fifo = value;
         } else {
             let mut param_count = self.cmd_fifo_param_count;
-            let len = FIFO_PARAM_COUNTS[(self.gx_fifo & 0x7F) as usize - 0x10];
-            self.queue_entry(Entry::new_with_len(self.gx_fifo as u8, len, value & mask));
+            let len = unsafe { *FIFO_PARAM_COUNTS.get_unchecked((self.gx_fifo & 0x7F) as usize - 0x10) };
+            self.queue_entry(Entry::new_with_len(self.gx_fifo as u8, len, value));
             param_count += 1;
 
             if param_count == len {
@@ -1381,14 +1382,24 @@ impl Gpu3DRegisters {
             }
         }
 
-        for _ in 0..4 {
-            if self.gx_fifo == 0 || FIFO_PARAM_COUNTS[(self.gx_fifo & 0x7F) as usize - 0x10] != 0 {
+        for _ in 0..4 - (self.gx_fifo.leading_zeros() >> 3) {
+            if unsafe { *FIFO_PARAM_COUNTS.get_unchecked((self.gx_fifo & 0x7F) as usize - 0x10) } != 0 {
                 break;
             }
-            self.queue_entry(Entry::new_with_len(self.gx_fifo as u8, 0, value & mask));
+            self.queue_entry(Entry::new_with_len(self.gx_fifo as u8, 0, 0));
             self.gx_fifo >>= 8;
         }
+    }
 
+    pub fn set_gx_fifo(&mut self, mask: u32, value: u32, emu: &mut Emu) {
+        self.queue_packed_value(value & mask);
+        self.post_queue_entry(emu);
+    }
+
+    pub fn set_gx_fifo_multiple(&mut self, values: &[u32], emu: &mut Emu) {
+        for &value in values {
+            self.queue_packed_value(value);
+        }
         self.post_queue_entry(emu);
     }
 

diff --git a/src/core/memory/dma.rs b/src/core/memory/dma.rs
@@ -1,6 +1,6 @@
 use crate::core::cpu_regs::InterruptFlag;
 use crate::core::cycle_manager::{CycleManager, EventType};
-use crate::core::emu::{get_cm_mut, get_common, get_cpu_regs_mut, get_mem_mut, io_dma, io_dma_mut, Emu};
+use crate::core::emu::{get_cm_mut, get_common, get_common_mut, get_cpu_regs_mut, get_mem_mut, io_dma, io_dma_mut, Emu};
 use crate::core::CpuType;
 use crate::logging::debug_println;
 use crate::utils;
@@ -275,14 +275,21 @@ impl Dma {
 
         let dma = io_dma_mut!(emu, CPU);
         let total_size = count << (step_size >> 1);
-        dma.src_buf.resize(total_size as usize, 0);
+        if dma.src_buf.len() < total_size as usize {
+            dma.src_buf.resize(total_size as usize, 0);
+        }
 
         match (src_addr_ctrl, dest_addr_ctrl) {
             (DmaAddrCtrl::Increment, DmaAddrCtrl::Fixed) => {
                 let mem = get_mem_mut!(emu);
                 let slice = unsafe { slice::from_raw_parts_mut(dma.src_buf.as_mut_ptr() as *mut T, count as usize) };
                 mem.read_multiple_slice::<CPU, false, T>(*src_addr, emu, slice);
-                mem.write_fixed_slice::<CPU, false, T>(*dest_addr, emu, slice);
+                if *dest_addr >= 0x4000400 && *dest_addr < 0x4000440 {
+                    let slice = unsafe { slice::from_raw_parts(slice.as_ptr() as *const u32, (total_size as usize) >> 2) };
+                    get_common_mut!(emu).gpu.gpu_3d_regs.set_gx_fifo_multiple(slice, emu);
+                } else {
+                    mem.write_fixed_slice::<CPU, false, T>(*dest_addr, emu, slice);
+                }
                 *src_addr += total_size;
             }
             (DmaAddrCtrl::Increment, DmaAddrCtrl::Increment | DmaAddrCtrl::IncrementReload) => {