Main Memory Management

[giuliof]

With last commit (c1664cf) should be clearer how main memory is addressed and where all these ram chips are placed. There is a block diagram attached which I hope can give some more info.

• put actual chips in schematics. Auxiliary RAM and ROM are missing and should be added somewhere.
• verify wiring. Some connections should be checked twice with continuity tests, in particular addresses connected to H2/H3 buffers and J2/J3 mux, DRAM placements, ...
• parity generator is not yet completed, and I suspect that parity error triggers some kind of interrupt.
• video memory, but this is another task.

Feel free to add more notes regarding main memory management to this issue.

[giuliof]

Updated schematic