Add RAM module

run.py

@@ -16,7 +16,6 @@
 
 # Add all files ending in .vhd in current working directory to library
 lib.add_source_files("src/*.vhd")
-lib.add_source_files("src/CPU/*.vhd")
 lib.add_source_files("src/sim/*.vhd")
 
 # Run vunit function

sap_1.gprj.user

@@ -4,14 +4,21 @@
     <Version>1.0</Version>
     <FlowState>
         <Process ID="Synthesis" State="2"/>
-        <Process ID="Pnr" State="0"/>
-        <Process ID="Gao" State="0"/>
+        <Process ID="Pnr" State="2"/>
+        <Process ID="Gao" State="2"/>
         <Process ID="Rtl_Gao" State="2"/>
     </FlowState>
     <ResultFileList>
         <ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/sap_1.vg"/>
+        <ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/sap_1.fs"/>
+        <ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/sap_1.pin.html"/>
+        <ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/sap_1.db"/>
+        <ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/sap_1.power.html"/>
+        <ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/sap_1.rpt.html"/>
+        <ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/sap_1.timing_paths"/>
+        <ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/sap_1.tr.html"/>
         <ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/sap_1_syn.rpt.html"/>
         <ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/sap_1_syn_rsc.xml"/>
     </ResultFileList>
-    <Ui>000000ff00000001fd00000002000000000000010000000182fc0200000001fc0000003f000001820000009a01000018fa000000000200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006600fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000006200fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000008100ffffff000000030000050000000110fc0100000001fc00000000000005000000009e00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004d00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009e00ffffff000003fa0000018200000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000b6ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000195ffffffff0000000000000000ffffffff0100000264ffffffff0000000000000000</Ui>
+    <Ui>000000ff00000001fd0000000200000000000001000000025ffc0200000001fc0000003f0000025f0000009a01000018fa000000010200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006600fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000006200fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000008100ffffff000000030000050000000110fc0100000001fc00000000000005000000009e00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004d00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009e00ffffff000003fa0000025f00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000b6ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000195ffffffff0000000000000000ffffffff0100000264ffffffff0000000000000000</Ui>
 </UserConfig>

src/RAM.vhd

@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity RAM is
+    port (
+        i_Clk : in std_logic;
+        i_Addr : in std_logic_vector(3 downto 0);
+        i_Data : in std_logic_vector(7 downto 0);
+        i_Write : in std_logic;
+        o_Data : out std_logic_vector(7 downto 0)
+    );
+end entity RAM;
+
+architecture rtl of RAM is
+    type ram_type is array(0 to 15) of std_logic_vector(7 downto 0);
+    signal r_RAM : ram_type := (others => (others => '0'));
+begin
+    process (i_Clk)
+    begin
+        if rising_edge(i_Clk) then
+            if i_Write = '1' then
+                r_RAM(to_integer(unsigned(i_Addr))) <= i_Data;
+            end if;
+            o_Data <= r_RAM(to_integer(unsigned(i_Addr)));
+        end if;
+    end process;
+end rtl;

src/SAP_1_Top.vhd

@@ -10,9 +10,30 @@ entity sap_1_top is
 end entity sap_1_top;
 
 architecture rtl of sap_1_top is
-    signal w_Clk : std_logic;
-    signal r_Clk_En : std_logic;
-begin  
+    signal w_Clk : std_logic; -- Internal clock signal
+    signal r_Clk_En : std_logic; -- Clock enable signal
+
+    -- Registers
+    signal r_Reg_A : std_logic_vector(7 downto 0); -- General purpose register A
+    signal r_Reg_B : std_logic_vector(7 downto 0); -- General purpose register B
+    signal r_Reg_MAR : std_logic_vector(3 downto 0); -- Memory address register (4-bit)
+
+    -- ALU
+    signal w_ALU_Out : std_logic_vector(7 downto 0); -- Output of the ALU
+
+    -- RAM
+    signal w_RAM_Out : std_logic_vector(7 downto 0); -- Output of the RAM
+    signal w_RAM_Write : std_logic; -- Write signal for the RAM
+
+    -- Bus
+    signal w_Bus : std_logic_vector(7 downto 0);
+    signal r_Bus_Enable_ALU : std_logic := '0'; -- Enable the bus to be driven by the ALU
+    signal r_Bus_Enable_RAM : std_logic := '0'; -- Enable the bus to be driven by the RAM
+
+    -- Flags
+    signal w_Carry : std_logic; -- Carry flag (set if the ALU operation results in a carry)
+    signal w_Subtract : std_logic; -- Subtract flag (set if the ALU operation is a subtraction)
+begin
 
     -- Generate the clock signal using a divider
     Clock_Inst : entity work.clock_divider
@@ -26,4 +47,29 @@ begin
             i_Reset => '0'
         );
 
+    -- ALU
+    ALU_Inst : entity work.ALU
+        port map(
+            i_A => r_Reg_A,
+            i_B => r_Reg_B,
+            o_Out => w_ALU_Out,
+            o_Carry => w_Carry,
+            i_Subtract => w_Subtract
+        );
+
+    -- RAM
+    RAM_Inst : entity work.RAM
+        port map(
+            i_Clk => w_Clk,
+            i_Addr => r_Reg_MAR,
+            i_Data => w_Bus,
+            o_Data => w_RAM_Out,
+            i_Write => w_RAM_Write
+        );
+
+    -- Bus
+    w_Bus <= w_ALU_Out when r_Bus_Enable_ALU = '1' else
+        w_RAM_Out when r_Bus_Enable_RAM = '1' else
+        (others => 'Z');
+
 end rtl;

src/sim/RAM_TB.vhd

@@ -0,0 +1,101 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library vunit_lib;
+context vunit_lib.vunit_context;
+
+entity RAM_TB is
+    generic (runner_cfg : string);
+end entity;
+
+architecture tb of RAM_TB is
+
+    signal r_Clk : std_logic := '0';
+    signal r_Reg_MAR : std_logic_vector(3 downto 0) := (others => '0');
+    signal r_Bus : std_logic_vector(7 downto 0) := (others => '0');
+    signal w_RAM_Out : std_logic_vector(7 downto 0);
+    signal r_RAM_Write : std_logic := '0';
+
+begin
+    -- Instantiate the UUT
+    UUT : entity work.RAM
+        port map(
+            i_Clk => r_Clk,
+            i_Addr => r_Reg_MAR,
+            i_Data => r_Bus,
+            o_Data => w_RAM_Out,
+            i_Write => r_RAM_Write
+        );
+
+    -- Clock
+    -- r_Clk <= not r_Clk after 5 ns;
+
+    main : process
+    begin
+        test_runner_setup(runner, runner_cfg);
+        r_Clk <= '0';
+        wait for 10 ns;
+        r_Clk <= '1';
+        wait for 10 ns;
+
+        -- Simulation starts here
+
+        -- Check all addresses should be 0
+        for i in 0 to 15 loop
+            r_Reg_MAR <= std_logic_vector(to_unsigned(i, 4));
+            r_RAM_Write <= '0';
+            wait for 10 ns;
+            r_Clk <= '0';
+            wait for 10 ns;
+            r_Clk <= '1';
+            wait for 10 ns;
+            assert w_RAM_Out = "00000000" report "RAM output is not 0" severity failure;
+        end loop;
+
+        -- Write to RAM
+        wait for 10 ns;
+        r_RAM_Write <= '1';
+        r_Reg_MAR <= "0000";
+        r_Bus <= "10101010";
+        wait for 10 ns;
+        r_Clk <= '0';
+        wait for 10 ns;
+        r_Clk <= '1';
+        wait for 10 ns;
+
+        -- Write to another location
+        r_RAM_Write <= '1';
+        r_Reg_MAR <= "1111";
+        r_Bus <= "01010101";
+        wait for 10 ns;
+        r_Clk <= '0';
+        wait for 10 ns;
+        r_Clk <= '1';
+        wait for 10 ns;
+
+        -- Read from RAM
+        r_RAM_Write <= '0';
+        r_Reg_MAR <= "0000";
+        wait for 10 ns;
+        r_Clk <= '0';
+        wait for 10 ns;
+        r_Clk <= '1';
+        wait for 10 ns;
+        assert w_RAM_Out = "10101010" report "RAM output is not 10101010" severity failure;
+
+        -- Read from another location
+        r_RAM_Write <= '0';
+        r_Reg_MAR <= "1111";
+        wait for 10 ns;
+        r_Clk <= '0';
+        wait for 10 ns;
+        r_Clk <= '1';
+        wait for 10 ns;
+        assert w_RAM_Out = "01010101" report "RAM output is not 01010101" severity failure;
+
+        wait for 10 ns;
+
+        test_runner_cleanup(runner); -- Simulation ends here
+    end process;
+end architecture;