Full 8-bit adder implemented

(with subtraction flag)
Fede-26 · Feb 18, 2024 · 4532888 · 4532888
1 parent c2998e3
commit 4532888
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Showing 6 changed files with 123 additions and 13 deletions.
diff --git a/run.py b/run.py
@@ -16,6 +16,7 @@
 
 # Add all files ending in .vhd in current working directory to library
 lib.add_source_files("src/*.vhd")
+lib.add_source_files("src/CPU/*.vhd")
 lib.add_source_files("src/sim/*.vhd")
 
 # Run vunit function

diff --git a/sap_1.gprj b/sap_1.gprj
@@ -5,6 +5,7 @@
     <Version>5</Version>
     <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
     <FileList>
+        <File path="src/CPU/ALU.vhd" type="file.vhdl" enable="1"/>
         <File path="src/Clock_Divider.vhd" type="file.vhdl" enable="1"/>
         <File path="src/SAP_1_Top.vhd" type="file.vhdl" enable="1"/>
     </FileList>

diff --git a/sap_1.gprj.user b/sap_1.gprj.user
@@ -4,21 +4,14 @@
     <Version>1.0</Version>
     <FlowState>
         <Process ID="Synthesis" State="2"/>
-        <Process ID="Pnr" State="2"/>
-        <Process ID="Gao" State="2"/>
+        <Process ID="Pnr" State="0"/>
+        <Process ID="Gao" State="0"/>
         <Process ID="Rtl_Gao" State="2"/>
     </FlowState>
     <ResultFileList>
         <ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/sap_1.vg"/>
-        <ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/sap_1.fs"/>
-        <ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/sap_1.pin.html"/>
-        <ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/sap_1.db"/>
-        <ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/sap_1.power.html"/>
-        <ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/sap_1.rpt.html"/>
-        <ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/sap_1.timing_paths"/>
-        <ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/sap_1.tr.html"/>
         <ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/sap_1_syn.rpt.html"/>
         <ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/sap_1_syn_rsc.xml"/>
     </ResultFileList>
-    <Ui>000000ff00000001fd00000002000000000000010000000288fc0200000001fc0000003f000002880000009a01000018fa000000020200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006600fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000006200fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000008100ffffff000000030000078000000110fc0100000001fc00000000000007800000009e00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004d00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009e00ffffff0000067a0000028800000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000b6ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000195ffffffff0000000000000000ffffffff0100000264ffffffff0000000000000000</Ui>
+    <Ui>000000ff00000001fd00000002000000000000010000000182fc0200000001fc0000003f000001820000009a01000018fa000000000200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006600fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000006200fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000008100ffffff000000030000050000000110fc0100000001fc00000000000005000000009e00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004d00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009e00ffffff000003fa0000018200000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000b6ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000195ffffffff0000000000000000ffffffff0100000264ffffffff0000000000000000</Ui>
 </UserConfig>
diff --git a/src/CPU/ALU.vhd b/src/CPU/ALU.vhd
@@ -0,0 +1,29 @@
+-- Inspired by the pinout of DM74LS283, 4-bit binary full adder with fast carry
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ALU is
+    port (
+        i_A, i_B : in std_logic_vector(7 downto 0); -- 8-bit input registers
+        o_Out : out std_logic_vector(7 downto 0); -- 8-bit output register
+        o_Carry : out std_logic; -- Carry output
+        i_Subtract : in std_logic -- Subtract flag (if 1, subtract, if 0, add)
+    );
+end ALU;
+
+architecture rtl of ALU is
+    signal w_Carry_Tmp : std_logic_vector(8 downto 0);
+    signal w_B: std_logic_vector(7 downto 0);
+begin
+
+    w_B <= std_logic_vector(unsigned(not i_B) + 1) when i_Subtract = '1' else i_B; -- Two's complement
+
+    o_Out <= std_logic_vector(unsigned(i_A) + unsigned(w_B));
+
+    -- o_Out <= std_logic_vector(unsigned(i_A) + unsigned(i_B)) when i_Subtract = '0' else std_logic_vector(unsigned(i_A) - unsigned(i_B));
+
+    w_Carry_Tmp <= std_logic_vector(unsigned('0' & i_A) + unsigned('0' & i_B));
+    o_Carry <= w_Carry_Tmp(8);
+end rtl;
diff --git a/src/SAP_1_Top.vhd b/src/SAP_1_Top.vhd
@@ -12,7 +12,7 @@ end entity sap_1_top;
 architecture rtl of sap_1_top is
     signal w_Clk : std_logic;
     signal r_Clk_En : std_logic;
-begin
+begin  
 
     -- Generate the clock signal using a divider
     Clock_Inst : entity work.clock_divider
@@ -26,6 +26,4 @@ begin
             i_Reset => '0'
         );
 
-
-
 end rtl;
diff --git a/src/sim/ALU_TB.vhd b/src/sim/ALU_TB.vhd
@@ -0,0 +1,88 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library vunit_lib;
+context vunit_lib.vunit_context;
+
+entity ALU_TB is
+    generic (runner_cfg : string);
+end entity;
+
+architecture tb of ALU_TB is
+
+    function num(val : in integer) return std_logic_vector is
+    begin
+        return std_logic_vector(to_unsigned(val, 8));
+    end function num;
+
+    signal w_A, w_B, w_Out : std_logic_vector(7 downto 0);
+    signal w_Carry : std_logic;
+    signal r_Subtract : std_logic := '0';
+begin
+    -- Instantiate the UUT
+    UUT : entity work.ALU
+        port map(
+            i_A => w_A,
+            i_B => w_B,
+            o_Out => w_Out,
+            o_Carry => w_Carry,
+            i_Subtract => r_Subtract
+        );
+
+    main : process
+    begin
+        test_runner_setup(runner, runner_cfg);
+
+        -- Simulation starts here
+        w_A <= num(1);
+        w_B <= num(1);
+        wait for 10 ns;
+        assert w_Out = num(2) report "Error: 1 + 1 != 2" severity failure;
+        assert w_Carry = '0' report "Error: carry set" severity failure;
+
+        w_A <= num(3); -- Dec -1
+        w_B <= num(5); -- Dec 3
+        wait for 10 ns;
+        assert w_Out = num(8) report "Error: 3 + 5 != 8" severity failure;
+        assert w_Carry = '0' report "Error: carry set" severity failure;
+
+        w_A <= num(255);
+        w_B <= num(1);
+        wait for 10 ns;
+        assert w_Out = num(0) report "Error: 0xFF + 0x01 != 0x00" severity failure;
+        assert w_Carry = '1' report "Error: carry not set" severity failure;
+
+        w_A <= num(255);
+        w_B <= num(255);
+        wait for 10 ns;
+        assert w_Out = num(254) report "Error: 0xFF + 0xFF != 0xFE" severity failure;
+        assert w_Carry = '1' report "Error: carry not set" severity failure;
+
+        w_A <= "01111111"; -- Dec 127
+        w_B <= "00000001"; -- Dec 1
+        wait for 10 ns;
+        assert w_Out = "10000000" report "Error: 127 + 1 != 128" severity failure;
+        assert w_Carry = '0' report "Error: carry set" severity failure;
+
+        -- Subtraction
+        r_Subtract <= '1';
+        wait for 10 ns;
+
+        w_A <= "00000011";
+        w_B <= "00000010";
+        wait for 10 ns;
+        assert w_Out = "00000001" report "Error: 3 - 2 != 1" severity failure;
+        assert w_Carry = '0' report "Error: carry set" severity failure;
+
+        w_A <= "11000000";
+        w_B <= "11111110";
+        wait for 10 ns;
+        assert w_Out = "11000010" report "Error: (-64) - (-2) != (-62)" severity failure;
+        assert w_Carry = '1' report "Error: carry set" severity failure;
+
+        wait for 10 ns;
+
+        test_runner_cleanup(runner); -- Simulation ends here
+    end process;
+end architecture;