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A bit of cleanup on the opmap generating code
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@CensoredUsername
CensoredUsername committed Aug 21, 2019
1 parent 10fe590 commit b1187e0
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Showing 8 changed files with 219 additions and 170 deletions.
4 changes: 2 additions & 2 deletions build_docs.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -35,11 +35,11 @@ cat ./doc/hack.js >> ./build_docs/plugin/search-index.js
cat ./doc/hack.js >> ./build_docs/runtime/search-index.js

echo "copy docs examples to tests"
declare -a examples=("bf-interpreter" "bf-jit" "hello-world")
declare -a examples=("bf-jit" "hello-world")
for EX in "${examples[@]}"
do
TARGET=$(echo $EX | tr - _)
cp "./doc/examples/${EX}/src/main.rs" "./testing/tests/${TARGET}.rs"
cp "./doc/examples/${EX}/src/x64.rs" "./testing/tests/${TARGET}.rs"
echo -n -e "#[test]\nfn ex_${TARGET}()\n{\n main();\n}\n" >> \
"./testing/tests/${TARGET}.rs"
done
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3 changes: 3 additions & 0 deletions plugin/src/arch/aarch64/aarch64data.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,9 @@ pub enum Matcher {
RefPre,
RefIndex,

// a single modifier
LitMod(Modifier),

// a set of allowed modifiers
Mod(&'static [Modifier]),

Expand Down
38 changes: 38 additions & 0 deletions plugin/src/arch/aarch64/ast.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -222,6 +222,44 @@ pub enum Modifier {
MSL,
}

impl Modifier {
pub fn as_str(&self) -> &'static str {
match self {
Modifier::LSL => "LSL",
Modifier::LSR => "LSR",
Modifier::ASR => "ASR",
Modifier::ROR => "ROR",
Modifier::SXTX => "SXTX",
Modifier::SXTW => "SXTW",
Modifier::SXTH => "SXTH",
Modifier::SXTB => "SXTB",
Modifier::UXTX => "UXTX",
Modifier::UXTW => "UXTW",
Modifier::UXTH => "UXTH",
Modifier::UXTB => "UXTB",
Modifier::MSL => "MSL",
}
}

pub fn expr_required(&self) -> bool {
match self {
Modifier::LSL
| Modifier::LSR
| Modifier::ASR
| Modifier::ROR
| Modifier::MSL => true,
Modifier::SXTX
| Modifier::SXTW
| Modifier::SXTH
| Modifier::SXTB
| Modifier::UXTX
| Modifier::UXTW
| Modifier::UXTH
| Modifier::UXTB => false,
}
}
}

#[derive(Debug, Clone)]
pub struct ModifyExpr {
pub op: Modifier,
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196 changes: 101 additions & 95 deletions plugin/src/arch/aarch64/debug.rs
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18 changes: 10 additions & 8 deletions plugin/src/arch/aarch64/matching.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -65,12 +65,9 @@ fn sanitize_args(args: Vec<RawArg>) -> Result<Vec<CleanArg>, Option<String>> {
// modifier: LSL LSR ASR ROR and MSL require an immediate.
RawArg::Modifier { span, modifier } => {
if modifier.expr.is_none() {
match modifier.op {
Modifier::LSL | Modifier::LSR | Modifier::ASR | Modifier::ROR | Modifier::MSL => {
emit_error_at(span, "LSL, LSR, ASR, ROR and MSL modifiers require a shift immediate.".into());
return Err(None);
}
_ => ()
if modifier.op.expr_required() {
emit_error_at(span, "LSL, LSR, ASR, ROR and MSL modifiers require a shift immediate.".into());
return Err(None);
}
}

Expand Down Expand Up @@ -174,7 +171,7 @@ fn sanitize_args(args: Vec<RawArg>) -> Result<Vec<CleanArg>, Option<String>> {
}

// LSL requires a stated immediate
if m.op == Modifier::LSL && m.expr.is_none() {
if m.op.expr_required() && m.expr.is_none() {
emit_error_at(span, "LSL reference modifier requires an immediate".into());
return Err(None);
}
Expand Down Expand Up @@ -479,6 +476,8 @@ impl Matcher {
CleanArg::Modifier { modifier, .. } => {
if let Matcher::Mod(list) = self {
list.iter().any(|m| m == &modifier.op)
} else if let Matcher::LitMod(m) = self {
m == &modifier.op
} else {
false
}
Expand Down Expand Up @@ -524,6 +523,7 @@ impl Matcher {
Matcher::RefPre => 2,
Matcher::RefIndex => 4,
Matcher::Mod(_) => 2,
Matcher::LitMod(_) => 1,

// this is special anyway
Matcher::End => 0,
Expand Down Expand Up @@ -619,7 +619,9 @@ fn flatten_args(args: Vec<CleanArg>, data: &Opdata, ctx: &mut MatchData) {
new_args.push(FlatArg::Immediate { value } );
},
CleanArg::Modifier { span, modifier } => {
new_args.push(FlatArg::Modifier { span, modifier: modifier.op } );
if arg_count >= 2 {
new_args.push(FlatArg::Modifier { span, modifier: modifier.op } );
}
if let Some(expr) = modifier.expr {
new_args.push(FlatArg::Immediate { value: expr });
}
Expand Down
58 changes: 29 additions & 29 deletions plugin/src/arch/aarch64/opmap.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -25,8 +25,8 @@ Ops!(map ;
0b10001011_00100000_00000000_00000000 = [XSP, XSP, W, End, Mod(EXTENDS_W)] => [R(0), R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
0b10001011_00100000_00000000_00000000 = [XSP, XSP, X, End, Mod(EXTENDS_X)] => [R(0), R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
// ADD (immediate)
0b00010001_00000000_00000000_00000000 = [WSP, WSP, Imm, End, Mod(&[LSL])] => [R(0), R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b10010001_00000000_00000000_00000000 = [XSP, XSP, Imm, End, Mod(&[LSL])] => [R(0), R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b00010001_00000000_00000000_00000000 = [WSP, WSP, Imm, End, LitMod(LSL)] => [R(0), R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
0b10010001_00000000_00000000_00000000 = [XSP, XSP, Imm, End, LitMod(LSL)] => [R(0), R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
// ADD (vector)
0b01011110_11100000_10000100_00000000 = [D, D, D] => [R(0), R(5), R(16)];
0b00001110_00100000_10000100_00000000 = [V(BYTE), V(BYTE), V(BYTE)] => [R(0), R(5), R(16), Rwidth(30)];
Expand Down Expand Up @@ -62,8 +62,8 @@ Ops!(map ;
0b10101011_00100000_00000000_00000000 = [X, XSP, W, End, Mod(EXTENDS_W)] => [R(0), R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
0b10101011_00100000_00000000_00000000 = [X, XSP, X, End, Mod(EXTENDS_X)] => [R(0), R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
// ADDS (immediate)
0b00110001_00000000_00000000_00000000 = [W, WSP, Imm, End, Mod(&[LSL])] => [R(0), R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b10110001_00000000_00000000_00000000 = [X, XSP, Imm, End, Mod(&[LSL])] => [R(0), R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b00110001_00000000_00000000_00000000 = [W, WSP, Imm, End, LitMod(LSL)] => [R(0), R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
0b10110001_00000000_00000000_00000000 = [X, XSP, Imm, End, LitMod(LSL)] => [R(0), R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
]
"addv" = [
0b00001110_00110001_10111000_00000000 = [B, V(BYTE)] => [R(0), R(5), Rwidth(30)];
Expand Down Expand Up @@ -190,8 +190,8 @@ Ops!(map ;
]
"bic" = [
// BIC (vector, immediate)
0b00101111_00000000_10010100_00000000 = [V(WORD), Imm, End, Mod(&[LSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, Ulist(13, &[0, 8])];
0b00101111_00000000_00010100_00000000 = [V(DWORD), Imm, End, Mod(&[LSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, Ulist(13, &[0, 8, 16, 24])];
0b00101111_00000000_10010100_00000000 = [V(WORD), Imm, End, LitMod(LSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, Ulist(13, &[0, 8])];
0b00101111_00000000_00010100_00000000 = [V(DWORD), Imm, End, LitMod(LSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, Ulist(13, &[0, 8, 16, 24])];
// BIC (vector, register)
0b00001110_01100000_00011100_00000000 = [V(BYTE), V(BYTE), V(BYTE)] => [R(0), R(5), R(16), Rwidth(30)];
// BIC (shifted register)
Expand Down Expand Up @@ -441,8 +441,8 @@ Ops!(map ;
0b10101011_00100000_00000000_00011111 = [XSP, W, End, Mod(EXTENDS_W)] => [R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
0b10101011_00100000_00000000_00011111 = [XSP, X, End, Mod(EXTENDS_X)] => [R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
// CMN (immediate)
0b00110001_00000000_00000000_00011111 = [WSP, Imm, End, Mod(&[LSL])] => [R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b10110001_00000000_00000000_00011111 = [XSP, Imm, End, Mod(&[LSL])] => [R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b00110001_00000000_00000000_00011111 = [WSP, Imm, End, LitMod(LSL)] => [R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
0b10110001_00000000_00000000_00011111 = [XSP, Imm, End, LitMod(LSL)] => [R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
]
"cmp" = [
// CMP (shifted register)
Expand All @@ -453,8 +453,8 @@ Ops!(map ;
0b11101011_00100000_00000000_00011111 = [XSP, W, End, Mod(EXTENDS_W)] => [R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
0b11101011_00100000_00000000_00011111 = [XSP, X, End, Mod(EXTENDS_X)] => [R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
// CMP (immediate)
0b01110001_00000000_00000000_00011111 = [WSP, Imm, End, Mod(&[LSL])] => [R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b11110001_00000000_00000000_00011111 = [XSP, Imm, End, Mod(&[LSL])] => [R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b01110001_00000000_00000000_00011111 = [WSP, Imm, End, LitMod(LSL)] => [R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
0b11110001_00000000_00000000_00011111 = [XSP, Imm, End, LitMod(LSL)] => [R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
]
"cmtst" = [
0b01011110_11100000_10001100_00000000 = [D, D, D] => [R(0), R(5), R(16)];
Expand Down Expand Up @@ -2300,24 +2300,24 @@ Ops!(map ;
0b01001110_00001000_00111100_00000000 = [X, VElement(QWORD)] => [R(0), R(5), Ubits(20, 1)];
]
"movi" = [
0b00001111_00000000_11100100_00000000 = [V(BYTE), Imm, End, Mod(&[LSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, BUbits(0), A, Rwidth(30)];
0b00001111_00000000_10000100_00000000 = [V(WORD), Imm, End, Mod(&[LSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, Ulist(13, &[0, 8]), Rwidth(30)];
0b00001111_00000000_00000100_00000000 = [V(DWORD), Imm, End, Mod(&[LSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, Ulist(13, &[0, 8, 16, 24]), Rwidth(30)];
0b00001111_00000000_11000100_00000000 = [V(DWORD), Imm, Mod(&[MSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, Ulist(12, &[8, 16]), Rwidth(30)];
0b00001111_00000000_11100100_00000000 = [V(BYTE), Imm, End, LitMod(LSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, BUbits(0), A, Rwidth(30)];
0b00001111_00000000_10000100_00000000 = [V(WORD), Imm, End, LitMod(LSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, Ulist(13, &[0, 8]), Rwidth(30)];
0b00001111_00000000_00000100_00000000 = [V(DWORD), Imm, End, LitMod(LSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, Ulist(13, &[0, 8, 16, 24]), Rwidth(30)];
0b00001111_00000000_11000100_00000000 = [V(DWORD), Imm, LitMod(MSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, Ulist(12, &[8, 16]), Rwidth(30)];
0b00101111_00000000_11100100_00000000 = [D, Imm] => [R(0), Special(5, STRETCHED_IMMEDIATE)];
0b01101111_00000000_11100100_00000000 = [VStatic(QWORD, 2), Imm] => [R(0), Special(5, STRETCHED_IMMEDIATE)];
]
"movk" = [
0b01110010_10000000_00000000_00000000 = [W, Imm, End, Mod(&[LSL])] => [R(0), Ubits(5, 16), A, Ulist(21, &[0, 16])];
0b11110010_10000000_00000000_00000000 = [X, Imm, End, Mod(&[LSL])] => [R(0), Ubits(5, 16), A, Ulist(21, &[0, 16, 32, 48])];
0b01110010_10000000_00000000_00000000 = [W, Imm, End, LitMod(LSL)] => [R(0), Ubits(5, 16), Ulist(21, &[0, 16])];
0b11110010_10000000_00000000_00000000 = [X, Imm, End, LitMod(LSL)] => [R(0), Ubits(5, 16), Ulist(21, &[0, 16, 32, 48])];
]
"movn" = [
0b00010010_10000000_00000000_00000000 = [W, Imm, End, Mod(&[LSL])] => [R(0), Ubits(5, 16), A, Ulist(21, &[0, 16])];
0b10010010_10000000_00000000_00000000 = [X, Imm, End, Mod(&[LSL])] => [R(0), Ubits(5, 16), A, Ulist(21, &[0, 16, 32, 48])];
0b00010010_10000000_00000000_00000000 = [W, Imm, End, LitMod(LSL)] => [R(0), Ubits(5, 16), Ulist(21, &[0, 16])];
0b10010010_10000000_00000000_00000000 = [X, Imm, End, LitMod(LSL)] => [R(0), Ubits(5, 16), Ulist(21, &[0, 16, 32, 48])];
]
"movz" = [
0b01010010_10000000_00000000_00000000 = [W, Imm, End, Mod(&[LSL])] => [R(0), Ubits(5, 16), A, Ulist(21, &[0, 16])];
0b11010010_10000000_00000000_00000000 = [X, Imm, End, Mod(&[LSL])] => [R(0), Ubits(5, 16), A, Ulist(21, &[0, 16, 32, 48])];
0b01010010_10000000_00000000_00000000 = [W, Imm, End, LitMod(LSL)] => [R(0), Ubits(5, 16), Ulist(21, &[0, 16])];
0b11010010_10000000_00000000_00000000 = [X, Imm, End, LitMod(LSL)] => [R(0), Ubits(5, 16), Ulist(21, &[0, 16, 32, 48])];
]
"mrs" = [
0b11010101_00110000_00000000_00000000 = [X, Imm] => [R(0), Ubits(5, 15)];
Expand Down Expand Up @@ -2350,9 +2350,9 @@ Ops!(map ;
0b00101110_00100000_01011000_00000000 = [V(WORD), V(WORD)] => [R(0), R(5), Rwidth(30)];
]
"mvni" = [
0b00101111_00000000_10000100_00000000 = [V(WORD), Imm, End, Mod(&[LSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, Ulist(13, &[0, 8]), Rwidth(30)];
0b00101111_00000000_00000100_00000000 = [V(DWORD), Imm, End, Mod(&[LSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, Ulist(13, &[0, 8, 16, 24]), Rwidth(30)];
0b00101111_00000000_11000100_00000000 = [V(DWORD), Imm, Mod(&[MSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, Ulist(12, &[8, 16]), Rwidth(30)];
0b00101111_00000000_10000100_00000000 = [V(WORD), Imm, End, LitMod(LSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, Ulist(13, &[0, 8]), Rwidth(30)];
0b00101111_00000000_00000100_00000000 = [V(DWORD), Imm, End, LitMod(LSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, Ulist(13, &[0, 8, 16, 24]), Rwidth(30)];
0b00101111_00000000_11000100_00000000 = [V(DWORD), Imm, LitMod(MSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, Ulist(12, &[8, 16]), Rwidth(30)];
]
"neg" = [
// NEG (shifted register)
Expand Down Expand Up @@ -2392,8 +2392,8 @@ Ops!(map ;
]
"orr" = [
// ORR (vector, immediate)
0b00001111_00000000_10010100_00000000 = [V(WORD), Imm, End, Mod(&[LSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, Ulist(13, &[0, 8])];
0b00001111_00000000_00010100_00000000 = [V(DWORD), Imm, End, Mod(&[LSL])] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, A, Ulist(13, &[0, 8, 16, 24])];
0b00001111_00000000_10010100_00000000 = [V(WORD), Imm, End, LitMod(LSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, Ulist(13, &[0, 8])];
0b00001111_00000000_00010100_00000000 = [V(DWORD), Imm, End, LitMod(LSL)] => [R(0), BUbits(8), Uslice(5, 5, 0), Uslice(16, 3, 5), A, Ulist(13, &[0, 8, 16, 24])];
// ORR (vector, register)
0b00001110_10100000_00011100_00000000 = [V(BYTE), V(BYTE), V(BYTE)] => [R(0), R(5), R(16), Rwidth(30)];
// ORR (immediate)
Expand Down Expand Up @@ -3784,8 +3784,8 @@ Ops!(map ;
0b11001011_00100000_00000000_00000000 = [XSP, XSP, W, End, Mod(EXTENDS_W)] => [R(0), R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
0b11001011_00100000_00000000_00000000 = [XSP, XSP, X, End, Mod(EXTENDS_X)] => [R(0), R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
// SUB (immediate)
0b01010001_00000000_00000000_00000000 = [WSP, WSP, Imm, End, Mod(&[LSL])] => [R(0), R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b11010001_00000000_00000000_00000000 = [XSP, XSP, Imm, End, Mod(&[LSL])] => [R(0), R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b01010001_00000000_00000000_00000000 = [WSP, WSP, Imm, End, LitMod(LSL)] => [R(0), R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
0b11010001_00000000_00000000_00000000 = [XSP, XSP, Imm, End, LitMod(LSL)] => [R(0), R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
// SUB (vector)
0b01111110_11100000_10000100_00000000 = [D, D, D] => [R(0), R(5), R(16)];
0b00101110_00100000_10000100_00000000 = [V(BYTE), V(BYTE), V(BYTE)] => [R(0), R(5), R(16), Rwidth(30)];
Expand All @@ -3812,8 +3812,8 @@ Ops!(map ;
0b11101011_00100000_00000000_00000000 = [X, XSP, W, End, Mod(EXTENDS_W)] => [R(0), R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
0b11101011_00100000_00000000_00000000 = [X, XSP, X, End, Mod(EXTENDS_X)] => [R(0), R(5), R(16), ExtendsX(13), Urange(10, 0, 4)];
// SUBS (immediate)
0b01110001_00000000_00000000_00000000 = [W, WSP, Imm, End, Mod(&[LSL])] => [R(0), R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b11110001_00000000_00000000_00000000 = [X, XSP, Imm, End, Mod(&[LSL])] => [R(0), R(5), Ubits(10, 12), A, Ulist(22, &[0, 12])];
0b01110001_00000000_00000000_00000000 = [W, WSP, Imm, End, LitMod(LSL)] => [R(0), R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
0b11110001_00000000_00000000_00000000 = [X, XSP, Imm, End, LitMod(LSL)] => [R(0), R(5), Ubits(10, 12), Ulist(22, &[0, 12])];
]
"suqadd" = [
0b01011110_00100000_00111000_00000000 = [B, B] => [R(0), R(5)];
Expand Down
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