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theaoqi committed Jul 12, 2023
2 parents a9a3284 + a46b5ac commit 0d6d37f
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Showing 652 changed files with 25,559 additions and 6,560 deletions.
68 changes: 53 additions & 15 deletions make/jdk/src/classes/build/tools/taglet/SealedGraph.java
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2022, 2023, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -145,11 +145,15 @@ String graph(TypeElement rootClass, Set<String> exports) {

static void traverse(State state, TypeElement node, Set<String> exports) {
state.addNode(node);
for (TypeElement subNode : permittedSubclasses(node, exports)) {
if (isInPublicApi(node, exports) && isInPublicApi(subNode, exports)) {
state.addEdge(node, subNode);
if (!(node.getModifiers().contains(Modifier.SEALED) || node.getModifiers().contains(Modifier.FINAL))) {
state.addNonSealedEdge(node);
} else {
for (TypeElement subNode : permittedSubclasses(node, exports)) {
if (isInPublicApi(node, exports) && isInPublicApi(subNode, exports)) {
state.addEdge(node, subNode);
}
traverse(state, subNode, exports);
}
traverse(state, subNode, exports);
}
}

Expand All @@ -158,13 +162,31 @@ private final class State {
private static final String LABEL = "label";
private static final String TOOLTIP = "tooltip";
private static final String LINK = "href";
private static final String STYLE = "style";

private final TypeElement rootNode;

private final StringBuilder builder;

private final Map<String, Map<String, String>> nodeStyleMap;
private final Map<String, Map<String, StyleItem>> nodeStyleMap;

private int nonSealedHierarchyCount = 0;

private sealed interface StyleItem {
String valueString();

record PlainString(String text) implements StyleItem {
@Override
public String valueString() {
return "\"" + text + "\"";
}
}
record HtmlString(String text) implements StyleItem {
@Override
public String valueString() {
return "<" + text + ">";
}
}
}

public State(TypeElement rootNode) {
this.rootNode = rootNode;
Expand All @@ -188,13 +210,9 @@ public State(TypeElement rootNode) {

public void addNode(TypeElement node) {
var styles = nodeStyleMap.computeIfAbsent(id(node), n -> new LinkedHashMap<>());
styles.put(LABEL, node.getSimpleName().toString());
styles.put(TOOLTIP, node.getQualifiedName().toString());
styles.put(LINK, relativeLink(node));
if (!(node.getModifiers().contains(Modifier.SEALED) || node.getModifiers().contains(Modifier.FINAL))) {
// This indicates that the hierarchy is not closed
styles.put(STYLE, "dashed");
}
styles.put(LABEL, new StyleItem.PlainString(node.getSimpleName().toString()));
styles.put(TOOLTIP, new StyleItem.PlainString(node.getQualifiedName().toString()));
styles.put(LINK, new StyleItem.PlainString(relativeLink(node)));
}

// A permitted class must be in the same package or in the same module.
Expand Down Expand Up @@ -223,12 +241,32 @@ public void addEdge(TypeElement node, TypeElement subNode) {
.append(lineSeparator());
}

public void addNonSealedEdge(TypeElement node) {
// prepare open node
var openNodeId = "open node #" + nonSealedHierarchyCount++;
var styles = nodeStyleMap.computeIfAbsent(openNodeId, n -> new LinkedHashMap<>());
styles.put(LABEL, new StyleItem.HtmlString("<I>&lt;any&gt;</I>"));
styles.put(TOOLTIP, new StyleItem.PlainString("Non-sealed Hierarchy"));

// add link to parent node
builder.append(" ")
.append('"')
.append(openNodeId)
.append('"')
.append(" -> ")
.append(quotedId(node))
.append(" ")
.append("[style=\"dashed\"]")
.append(";")
.append(lineSeparator());
}

public String render() {
nodeStyleMap.forEach((nodeName, styles) -> {
builder.append(" ")
.append('"').append(nodeName).append("\" ")
.append(styles.entrySet().stream()
.map(e -> e.getKey() + "=\"" + e.getValue() + "\"")
.map(e -> e.getKey() + "=" + e.getValue().valueString())
.collect(joining(" ", "[", "]")))
.append(lineSeparator());
});
Expand Down
4 changes: 2 additions & 2 deletions make/modules/jdk.jfr/Java.gmk
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
#
# Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2020, 2023, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
Expand All @@ -24,5 +24,5 @@
#

DISABLED_WARNINGS_java += exports
COPY := .xsd .xml .dtd
COPY := .xsd .xml .dtd .ini
JAVAC_FLAGS := -XDstringConcat=inline
12 changes: 3 additions & 9 deletions make/test/JtregNativeHotspot.gmk
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
#
# Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2015, 2023, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -99,11 +99,6 @@ NSK_GC_LOCK_JVMTI_INCLUDES := \
-I$(VM_TESTBASE_DIR)/nsk/share/native \
-I$(VM_TESTBASE_DIR)/nsk/share/jni

NSK_GC_LOCK_MALLOC_INCLUDES := \
-I$(VM_TESTBASE_DIR)/nsk/share/gc/lock/malloc \
-I$(VM_TESTBASE_DIR)/nsk/share/native \
-I$(VM_TESTBASE_DIR)/nsk/share/jni

NSK_GC_LOCK_JNI_INCLUDES := \
-I$(VM_TESTBASE_DIR)/nsk/share/gc/lock/jni \
-I$(VM_TESTBASE_DIR)/nsk/share/native \
Expand Down Expand Up @@ -179,8 +174,6 @@ BUILD_HOTSPOT_JTREG_LIBRARIES_CFLAGS_libnativeAndMH := $(MLVM_STRESS_INCLUDES)

BUILD_HOTSPOT_JTREG_LIBRARIES_CFLAGS_libJVMTIAllocLocker := $(NSK_GC_LOCK_JVMTI_INCLUDES)

BUILD_HOTSPOT_JTREG_LIBRARIES_CFLAGS_libMallocLocker := $(NSK_GC_LOCK_MALLOC_INCLUDES)

BUILD_HOTSPOT_JTREG_LIBRARIES_CFLAGS_libBooleanArrayCriticalLocker := $(NSK_GC_LOCK_JNI_INCLUDES)
BUILD_HOTSPOT_JTREG_LIBRARIES_CFLAGS_libByteArrayCriticalLocker := $(NSK_GC_LOCK_JNI_INCLUDES)
BUILD_HOTSPOT_JTREG_LIBRARIES_CFLAGS_libCharArrayCriticalLocker := $(NSK_GC_LOCK_JNI_INCLUDES)
Expand Down Expand Up @@ -874,7 +867,7 @@ BUILD_HOTSPOT_JTREG_EXECUTABLES_LIBS_exesigtest := -ljvm

ifeq ($(call isTargetOs, windows), true)
BUILD_HOTSPOT_JTREG_EXECUTABLES_CFLAGS_exeFPRegs := -MT
BUILD_HOTSPOT_JTREG_EXCLUDE += exesigtest.c libterminatedThread.c libTestJNI.c libCompleteExit.c libTestPsig.c libnativeStack.c
BUILD_HOTSPOT_JTREG_EXCLUDE += exesigtest.c libterminatedThread.c libTestJNI.c libCompleteExit.c libTestPsig.c libnativeStack.c exeGetCreatedJavaVMs.c
BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libatExit := jvm.lib
BUILD_HOTSPOT_JTREG_EXECUTABLES_LIBS_exedaemonDestroy := jvm.lib
else
Expand Down Expand Up @@ -1516,6 +1509,7 @@ else
BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libatExit += -ljvm
BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libCompleteExit += -lpthread
BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libnativeStack += -lpthread
BUILD_HOTSPOT_JTREG_EXECUTABLES_LIBS_exeGetCreatedJavaVMs := -ljvm -lpthread
endif

ifeq ($(ASAN_ENABLED), true)
Expand Down
60 changes: 4 additions & 56 deletions src/hotspot/cpu/aarch64/aarch64.ad
Original file line number Diff line number Diff line change
Expand Up @@ -664,11 +664,6 @@ reg_class method_reg(
R12, R12_H
);

// Class for heapbase register
reg_class heapbase_reg(
R27, R27_H
);

// Class for thread register
reg_class thread_reg(
R28, R28_H
Expand Down Expand Up @@ -1244,15 +1239,15 @@ source %{
// zero, compressed klass pointers doesn't use r27 after JDK-8234794
if (UseCompressedOops && (CompressedOops::ptrs_base() != NULL)) {
_NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(r27->as_VMReg()));
_NO_SPECIAL_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
_NO_SPECIAL_PTR_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
_NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(r27->as_VMReg()));
_NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(r27->as_VMReg()));
}

// r29 is not allocatable when PreserveFramePointer is on
if (PreserveFramePointer) {
_NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(r29->as_VMReg()));
_NO_SPECIAL_REG_mask.SUBTRACT(_FP_REG_mask);
_NO_SPECIAL_PTR_REG_mask.SUBTRACT(_FP_REG_mask);
_NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(r29->as_VMReg()));
_NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(r29->as_VMReg()));
}
}

Expand Down Expand Up @@ -5320,17 +5315,6 @@ operand iRegNNoSp()
interface(REG_INTER);
%}

// heap base register -- used for encoding immN0

operand iRegIHeapbase()
%{
constraint(ALLOC_IN_RC(heapbase_reg));
match(RegI);
op_cost(0);
format %{ %}
interface(REG_INTER);
%}

// Float Register
// Float register operands
operand vRegF()
Expand Down Expand Up @@ -15034,42 +15018,6 @@ instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
ins_pipe(ialu_reg);
%}

instruct convI2B(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr)
%{
match(Set dst (Conv2B src));
effect(KILL cr);

format %{
"cmpw $src, zr\n\t"
"cset $dst, ne"
%}

ins_encode %{
__ cmpw(as_Register($src$$reg), zr);
__ cset(as_Register($dst$$reg), Assembler::NE);
%}

ins_pipe(ialu_reg);
%}

instruct convP2B(iRegINoSp dst, iRegP src, rFlagsReg cr)
%{
match(Set dst (Conv2B src));
effect(KILL cr);

format %{
"cmp $src, zr\n\t"
"cset $dst, ne"
%}

ins_encode %{
__ cmp(as_Register($src$$reg), zr);
__ cset(as_Register($dst$$reg), Assembler::NE);
%}

ins_pipe(ialu_reg);
%}

instruct convD2F_reg(vRegF dst, vRegD src) %{
match(Set dst (ConvD2F src));

Expand Down
67 changes: 24 additions & 43 deletions src/hotspot/cpu/aarch64/aarch64_vector.ad
Original file line number Diff line number Diff line change
Expand Up @@ -5512,6 +5512,30 @@ instruct vmask_truecount_sve(iRegINoSp dst, pReg src) %{
ins_pipe(pipe_slow);
%}

// Combined rule for VectorMaskTrueCount (VectorStoreMask) when the vector element type is not T_BYTE.

instruct vstoremask_truecount_neon(iRegINoSp dst, vReg src, immI_gt_1 size, vReg vtmp) %{
match(Set dst (VectorMaskTrueCount (VectorStoreMask src size)));
effect(TEMP vtmp);
format %{ "vstoremask_truecount_neon $dst, $src\t# KILL $vtmp" %}
ins_encode %{
// Input "src" is a vector mask represented as lanes with
// 0/-1 as element values.
uint esize = (uint)$size$$constant;
if (esize == 8) {
__ addpd($vtmp$$FloatRegister, $src$$FloatRegister);
} else {
uint length_in_bytes = Matcher::vector_length_in_bytes(this, $src);
Assembler::SIMD_Arrangement arrangement = Assembler::esize2arrangement(esize,
/* isQ */ length_in_bytes == 16);
__ addv($vtmp$$FloatRegister, arrangement, $src$$FloatRegister);
}
__ smov($dst$$Register, $vtmp$$FloatRegister, __ B, 0);
__ neg($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}

// first true

instruct vmask_firsttrue_lt8e(iRegINoSp dst, vReg src, rFlagsReg cr) %{
Expand Down Expand Up @@ -5992,49 +6016,6 @@ instruct vblend_sve(vReg dst, vReg src1, vReg src2, pReg pg) %{
ins_pipe(pipe_slow);
%}

// ------------------------- Vector conditional move --------------------------

instruct vcmove_neon(vReg dst, vReg src1, vReg src2, immI cond, cmpOp copnd) %{
predicate(UseSVE == 0 ||
(VM_Version::use_neon_for_vector(Matcher::vector_length_in_bytes(n)) &&
n->in(1)->in(2)->get_int() != BoolTest::ne));
match(Set dst (CMoveVF (Binary copnd cond) (Binary src1 src2)));
match(Set dst (CMoveVD (Binary copnd cond) (Binary src1 src2)));
effect(TEMP_DEF dst);
format %{ "vcmove_neon.$copnd $dst, $src1, $src2\t# vector conditional move fp" %}
ins_encode %{
Assembler::Condition condition = to_assembler_cond((BoolTest::mask)$cond$$constant);
BasicType bt = Matcher::vector_element_basic_type(this);
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
assert(length_in_bytes == 8 || length_in_bytes == 16, "must be");
__ neon_compare($dst$$FloatRegister, bt, $src1$$FloatRegister,
$src2$$FloatRegister, condition, /* isQ */ length_in_bytes == 16);
__ bsl($dst$$FloatRegister, length_in_bytes == 16 ? __ T16B : __ T8B,
$src2$$FloatRegister, $src1$$FloatRegister);
%}
ins_pipe(pipe_slow);
%}

instruct vcmove_sve(vReg dst, vReg src1, vReg src2, immI cond, cmpOp copnd, pRegGov pgtmp) %{
predicate(!VM_Version::use_neon_for_vector(Matcher::vector_length_in_bytes(n)) ||
(UseSVE > 0 && n->in(1)->in(2)->get_int() == BoolTest::ne));
match(Set dst (CMoveVF (Binary copnd cond) (Binary src1 src2)));
match(Set dst (CMoveVD (Binary copnd cond) (Binary src1 src2)));
effect(TEMP pgtmp);
format %{ "vcmove_sve.$copnd $dst, $src1, $src2\t# vector conditional move fp. KILL $pgtmp" %}
ins_encode %{
assert(UseSVE > 0, "must be sve");
Assembler::Condition condition = to_assembler_cond((BoolTest::mask)$cond$$constant);
BasicType bt = Matcher::vector_element_basic_type(this);
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
__ sve_compare($pgtmp$$PRegister, bt, ptrue, $src1$$FloatRegister,
$src2$$FloatRegister, condition);
__ sve_sel($dst$$FloatRegister, __ elemType_to_regVariant(bt),
$pgtmp$$PRegister, $src2$$FloatRegister, $src1$$FloatRegister);
%}
ins_pipe(pipe_slow);
%}

// ------------------------------ Vector round ---------------------------------

// vector Math.round
Expand Down
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