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My attempt to write a NES emulator in Verilog.

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Name		Name	Last commit message	Last commit date
Latest commit History 169 Commits
.vscode		.vscode
asm		asm
assets		assets
cpp		cpp
data		data
py		py
ver		ver
.gitignore		.gitignore
Makefile		Makefile
Makefile.core		Makefile.core
README.md		README.md

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Q2A03

My attempt to write a NES emulator in Verilog.

This repo is very messy, and it is a companion repo to 2 other projects https://github.com/2bitsin/fpga_daughter_board and https://github.com/2bitsin/FPGAme.

It's being tested on a CycloneV 5CEFA5F23 board from QMTech

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My attempt to write a NES emulator in Verilog.

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