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Simplify the Verilog "inside" (from @flaviens) (#2776) #1075

Simplify the Verilog "inside" (from @flaviens) (#2776)

Simplify the Verilog "inside" (from @flaviens) (#2776) #1075

Triggered via push February 19, 2025 13:25
Status Success
Total duration 1h 13m 5s
Artifacts 8

ci.yml

on: push
build-riscv-tests
30m 55s
build-riscv-tests
Matrix: execute-riscv32-tests
Matrix: execute-riscv64-tests
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Artifacts

Produced during runtime
Name Size
veri-testharness.cv32a6_tests.cv32a65x
219 KB
veri-testharness.cv64a6_imafdc_tests.cv64a6_imafdc_sv39
2.26 MB
veri-testharness.cv64a6_imafdc_tests.cv64a6_imafdc_sv39_hpdcache
2.26 MB
veri-testharness.cv64a6_imafdc_tests.cv64a6_imafdc_sv39_hpdcache_wb
2.26 MB
veri-testharness.cv64a6_imafdc_tests.cv64a6_imafdc_sv39_wb
2.26 MB
veri-testharness.dv-riscv-arch-test.cv32a65x
10.4 MB
veri-testharness.dv-riscv-arch-test.cv64a6_imafdc_sv39_hpdcache
37.3 MB
veri-testharness.dv-riscv-arch-test.cv64a6_imafdc_sv39_hpdcache_wb
37.3 MB