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fpga: Change default burst for xilinx ips #34

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fpga: Change default burst for xilinx ips #34

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304ffc6
Introduce bender and fix some versioning mismatch.
May 6, 2024
6dc10ac
Fixing compile errors.
May 7, 2024
b090ead
Fixing an error on msiptw reported by Synopsys DC
May 14, 2024
906c72d
Fixing mismatch with apb2reg and DC compiler errors.
May 14, 2024
e2dc8ab
Renaming apb_to_reg to avoid conflicts
May 15, 2024
c9c50f4
Add include dir in bender manifest to fetch ASSERTs.
May 20, 2024
26ae5a8
Reintroduce the Assert calls.
May 20, 2024
58654e0
fpga: Change default burst for xilinx ips
CyrilKoe Jun 17, 2024
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Fixing an error on msiptw reported by Synopsys DC
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Your Name committed May 23, 2024
commit b090ead7ae7ba645cc848d7d4216fdf74bdd2f60
16 changes: 9 additions & 7 deletions rtl/translation_logic/rv_iommu_msiptw.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -398,18 +398,20 @@ module rv_iommu_msiptw #(
end
end : flat_seq

// States
typedef enum logic[1:0] {
MRIF_PTE, // 00
NOTICE_PTE, // 01
MRIF_ERROR // 10
} state_mrif_t;

//# MSI-MRIF
generate

// MRIF support enabled
if (MSITrans == rv_iommu::MSI_FLAT_MRIF) begin : gen_mrif_support

// States
typedef enum logic[1:0] {
MRIF_PTE, // 00
NOTICE_PTE, // 01
MRIF_ERROR // 10
} state_mrif_t;

state_mrif_t mrif_state_q, mrif_state_n;

// Read ports
Expand Down Expand Up @@ -565,4 +567,4 @@ module rv_iommu_msiptw #(
end : gen_mrif_support_disabled
endgenerate

endmodule
endmodule