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Update riscv/debug_defines (to sync with riscv-debug-spec commit 40b9a05) #973
Update riscv/debug_defines (to sync with riscv-debug-spec commit 40b9a05) #973
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Looks OK. Just to check, can you show some debug output that uses the new code?
I would suggest updating to a more recent version to include these changes: riscv/riscv-debug-spec#908, riscv/riscv-debug-spec#909. Please, note that |
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I made riscv/riscv-debug-spec#922 to address the checkpatch issue. When that merges, please update this PR. |
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Change-Id: Ie969866d1de83360a5f45e96e22108b58b8aa02f Signed-off-by: Kirill Radkin <[email protected]>
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I have few suggestions related to code structure or naming. Otherwise this looks good.
@@ -2,6 +2,12 @@ | |||
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#include "debug_defines.h" | |||
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enum riscv_debug_reg_show { |
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Please, could you give a descriptive name to this enum, e.g. display_mode
(or similar), rather than show
.
enum riscv_debug_reg_show { | |
enum riscv_debug_reg_display_mode { |
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Correction per kr-sc's comment: This change should go to the debug spec repository instead (riscv-debug-spec).
@@ -62,22 +62,35 @@ static uint64_t riscv_debug_reg_field_value(riscv_debug_reg_field_info_t field, | |||
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static unsigned int riscv_debug_reg_fields_to_s(char *buf, unsigned int offset, | |||
struct riscv_debug_reg_field_list_t (*get_next)(riscv_debug_reg_ctx_t contex), | |||
riscv_debug_reg_ctx_t context, uint64_t value) | |||
riscv_debug_reg_ctx_t context, uint64_t value, | |||
enum riscv_debug_reg_show show) |
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enum riscv_debug_reg_show show) | |
enum riscv_debug_reg_display_mode display_mode) |
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Same as above: This change should go to the debug spec repository instead (riscv-debug-spec).
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uint64_t field_value = riscv_debug_reg_field_value(list.field, value); | ||
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if (show == RISCV_DEBUG_REG_SHOW_ALL || | ||
(show == RISCV_DEBUG_REG_HIDE_UNNAMED_0 && | ||
(field_value != 0 || | ||
(list.field.values && list.field.values[0]))) || | ||
(show == RISCV_DEBUG_REG_HIDE_ALL_0 && field_value != 0)) { | ||
curr += get_len_or_sprintf(buf, curr, separator); | ||
curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context, | ||
field_value); | ||
separator = " "; | ||
} |
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The condition of the "if" is complex, which makes it hard to understand and modify. Please, could you simplify this whole part of the code - for example as shown below.
uint64_t field_value = riscv_debug_reg_field_value(list.field, value); | |
if (show == RISCV_DEBUG_REG_SHOW_ALL || | |
(show == RISCV_DEBUG_REG_HIDE_UNNAMED_0 && | |
(field_value != 0 || | |
(list.field.values && list.field.values[0]))) || | |
(show == RISCV_DEBUG_REG_HIDE_ALL_0 && field_value != 0)) { | |
curr += get_len_or_sprintf(buf, curr, separator); | |
curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context, | |
field_value); | |
separator = " "; | |
} | |
uint64_t field_value = riscv_debug_reg_field_value(list.field, value); | |
const bool isZero = (field_value == 0); | |
const bool isUnnamed = (!list.field.values) || (!list.field.values[0]); | |
if (display_mode == RISCV_DEBUG_REG_HIDE_UNNAMED_0 && isUnnamed && isZero) | |
// Don't display this field | |
continue; | |
if (display_mode == RISCV_DEBUG_REG_HIDE_ALL_0 && isZero) | |
// Don't display this field | |
continue; | |
// Show this field | |
curr += get_len_or_sprintf(buf, curr, separator); | |
curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context, | |
field_value); | |
separator = " "; | |
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Same as above: This change should go to the debug spec repository instead (riscv-debug-spec).
@JanMatCodasip I think that we need patch to debus spec with your suggestions. What if we merge this patch and make a subsequent update with your suggestions to debug spec and openocd later? |
Ah, when looking at the changes, I missed the fact that the files
Sure, I agree, let's merge this now as is. If you are happy with the suggested changes, I believe it would be good to apply them to the riscv-debug-spec repo. |
Change-Id: Ie969866d1de83360a5f45e96e22108b58b8aa02f