Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Update riscv/debug_defines (to sync with riscv-debug-spec commit 40b9a05) #973

Merged
merged 1 commit into from
Dec 11, 2023

Conversation

kr-sc
Copy link
Contributor

@kr-sc kr-sc commented Dec 4, 2023

Change-Id: Ie969866d1de83360a5f45e96e22108b58b8aa02f

timsifive
timsifive previously approved these changes Dec 5, 2023
Copy link
Collaborator

@timsifive timsifive left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Looks OK. Just to check, can you show some debug output that uses the new code?

@en-sc
Copy link
Collaborator

en-sc commented Dec 6, 2023

I would suggest updating to a more recent version to include these changes: riscv/riscv-debug-spec#908, riscv/riscv-debug-spec#909. Please, note that debug_reg_printer.[ch] should also be updated if the changes are included.

@kr-sc kr-sc force-pushed the kr-sc/update-debug-defines-os branch 2 times, most recently from 16f9630 to 02f7348 Compare December 6, 2023 12:22
@kr-sc kr-sc changed the title Update riscv/debug_defines (to sync with https://github.com/riscv/riscv-debug-spec/pull/902) Update riscv/debug_defines (to sync with riscv-debug-spec commit a992f2ea8) Dec 6, 2023
@kr-sc kr-sc force-pushed the kr-sc/update-debug-defines-os branch 2 times, most recently from f33f004 to 30a5323 Compare December 6, 2023 14:03
@kr-sc
Copy link
Contributor Author

kr-sc commented Dec 6, 2023

Looks OK. Just to check, can you show some debug output that uses the new code?

Before:

log_debug_reg(): [riscv.cpu] dtmcs=0x61 { version=1.0, dmistat=0, idle=0, dmireset=0, dtmhardreset=0, errinfo=not implemented, abits=6, }

After:

log_debug_reg(): [riscv.cpu] dtmcs=0x61 {version=1_0 errinfo=not_implemented abits=6}

@timsifive
Copy link
Collaborator

I made riscv/riscv-debug-spec#922 to address the checkpatch issue. When that merges, please update this PR.

@kr-sc kr-sc force-pushed the kr-sc/update-debug-defines-os branch from 30a5323 to 420e5d2 Compare December 7, 2023 17:53
@kr-sc kr-sc changed the title Update riscv/debug_defines (to sync with riscv-debug-spec commit a992f2ea8) Update riscv/debug_defines (to sync with riscv-debug-spec commit 40b9a05) Dec 7, 2023
Change-Id: Ie969866d1de83360a5f45e96e22108b58b8aa02f
Signed-off-by: Kirill Radkin <[email protected]>
@kr-sc kr-sc force-pushed the kr-sc/update-debug-defines-os branch from 420e5d2 to 84e6a4e Compare December 7, 2023 17:59
Copy link
Collaborator

@JanMatCodasip JanMatCodasip left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I have few suggestions related to code structure or naming. Otherwise this looks good.

@@ -2,6 +2,12 @@

#include "debug_defines.h"

enum riscv_debug_reg_show {
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Please, could you give a descriptive name to this enum, e.g. display_mode (or similar), rather than show.

Suggested change
enum riscv_debug_reg_show {
enum riscv_debug_reg_display_mode {

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Correction per kr-sc's comment: This change should go to the debug spec repository instead (riscv-debug-spec).

@@ -62,22 +62,35 @@ static uint64_t riscv_debug_reg_field_value(riscv_debug_reg_field_info_t field,

static unsigned int riscv_debug_reg_fields_to_s(char *buf, unsigned int offset,
struct riscv_debug_reg_field_list_t (*get_next)(riscv_debug_reg_ctx_t contex),
riscv_debug_reg_ctx_t context, uint64_t value)
riscv_debug_reg_ctx_t context, uint64_t value,
enum riscv_debug_reg_show show)
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Suggested change
enum riscv_debug_reg_show show)
enum riscv_debug_reg_display_mode display_mode)

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Same as above: This change should go to the debug spec repository instead (riscv-debug-spec).

Comment on lines +73 to +85

uint64_t field_value = riscv_debug_reg_field_value(list.field, value);

if (show == RISCV_DEBUG_REG_SHOW_ALL ||
(show == RISCV_DEBUG_REG_HIDE_UNNAMED_0 &&
(field_value != 0 ||
(list.field.values && list.field.values[0]))) ||
(show == RISCV_DEBUG_REG_HIDE_ALL_0 && field_value != 0)) {
curr += get_len_or_sprintf(buf, curr, separator);
curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context,
field_value);
separator = " ";
}
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The condition of the "if" is complex, which makes it hard to understand and modify. Please, could you simplify this whole part of the code - for example as shown below.

Suggested change
uint64_t field_value = riscv_debug_reg_field_value(list.field, value);
if (show == RISCV_DEBUG_REG_SHOW_ALL ||
(show == RISCV_DEBUG_REG_HIDE_UNNAMED_0 &&
(field_value != 0 ||
(list.field.values && list.field.values[0]))) ||
(show == RISCV_DEBUG_REG_HIDE_ALL_0 && field_value != 0)) {
curr += get_len_or_sprintf(buf, curr, separator);
curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context,
field_value);
separator = " ";
}
uint64_t field_value = riscv_debug_reg_field_value(list.field, value);
const bool isZero = (field_value == 0);
const bool isUnnamed = (!list.field.values) || (!list.field.values[0]);
if (display_mode == RISCV_DEBUG_REG_HIDE_UNNAMED_0 && isUnnamed && isZero)
// Don't display this field
continue;
if (display_mode == RISCV_DEBUG_REG_HIDE_ALL_0 && isZero)
// Don't display this field
continue;
// Show this field
curr += get_len_or_sprintf(buf, curr, separator);
curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context,
field_value);
separator = " ";

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Same as above: This change should go to the debug spec repository instead (riscv-debug-spec).

@kr-sc
Copy link
Contributor Author

kr-sc commented Dec 11, 2023

@JanMatCodasip I think that we need patch to debus spec with your suggestions. What if we merge this patch and make a subsequent update with your suggestions to debug spec and openocd later?

@JanMatCodasip
Copy link
Collaborator

JanMatCodasip commented Dec 11, 2023

kr-sc: I think that we need patch to debug spec with your suggestions.

Ah, when looking at the changes, I missed the fact that the files debug_reg_printer.* are auto-generated from the debug spec repository. Thank you for the reminder.

kr-sc: What if we merge this patch and make a subsequent update with your suggestions to debug spec and openocd later?

Sure, I agree, let's merge this now as is.

If you are happy with the suggested changes, I believe it would be good to apply them to the riscv-debug-spec repo.

@timsifive timsifive merged commit b5e0ec3 into riscv-collab:riscv Dec 11, 2023
4 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

4 participants