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target/riscv: refactored memory access result codes #1218

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@fk-sc fk-sc commented Jan 29, 2025

Slightly refactored memory access result codes:

  • Changed enum formatting
  • Changed status handlers to decrease boilerplate

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fk-sc commented Jan 29, 2025

This commit precedes the next commit, which introduces more precise/correct return codes.

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fk-sc commented Jan 29, 2025

@JanMatCodasip, @MarekVCodasip can you please take a look?

src/target/riscv/riscv-013.c Outdated Show resolved Hide resolved
src/target/riscv/riscv-013.c Outdated Show resolved Hide resolved
Slightly refactored memory access result codes:
* Changed enum formatting
* Changed status handlers to decrease boilerplate

Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Signed-off-by: Farid Khaydari <[email protected]>
@fk-sc fk-sc force-pushed the fk-sc/ref-mem-acc-res branch from 0366781 to 827d2af Compare January 29, 2025 15:54
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LGTM, thank you.

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