Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Update rggen.md #243

Open
wants to merge 1 commit into
base: develop
Choose a base branch
from
Open

Update rggen.md #243

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions content/items/rggen.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ RgGen has following features:

* Generate following source files for CSR automatically from register map specifications
* SystemVerilog/Verilog RTL
* [Veryl](https://veryl-lang.org) RTL
* VHDL RTL
* UVM register model (RAL)
* Markdown documents
Expand Down