Skip to content
View franhans's full-sized avatar

Block or report franhans

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. FPGA_Snake FPGA_Snake Public

    Snake Videogame for IceCore

    Verilog 1

  2. IceCore IceCore Public

    Forked from folknology/IceCore

    IceCore Ice40 HX based modular core

    C

  3. FPGA_UART FPGA_UART Public

    In this project I create a little UART (currently only the rx port and a 7 segments displayer) to the IceCore.

    Verilog

  4. FPGA_squareGame FPGA_squareGame Public

    FPGA verilog program which displays a VGA signal and recives commands through rx. With these two modules a little videogame is created.

    AGS Script

  5. riscv-probe riscv-probe Public

    Forked from michaeljclark/riscv-probe

    Simple machine mode program to probe RISC-V control and status registers

    C

  6. franhans franhans Public

    Config files for my GitHub profile.