5466 - introduce in_tag dispatching to the ALU

barretenberg/cpp/pil/avm/avm_main.pil

@@ -53,6 +53,8 @@ namespace avm_main(256);
     pol commit sel_op_or;
     // XOR
     pol commit sel_op_xor;
+    // CAST
+    pol commit sel_op_cast;
 
     // Helper selector to characterize an ALU chiplet selector
     pol commit alu_sel;
@@ -63,6 +65,7 @@ namespace avm_main(256);
     // Instruction memory tags read/write (1: u8, 2: u16, 3: u32, 4: u64, 5: u128, 6: field)
     pol commit r_in_tag;
     pol commit w_in_tag;
+    pol commit alu_in_tag; // Copy of r_in_tag or w_in_tag depending of the operation. It is sent to ALU trace.
 
     // Errors
     pol commit op_err; // Boolean flag pertaining to an operation error
@@ -97,21 +100,20 @@ namespace avm_main(256);
     pol commit ind_op_b;
     pol commit ind_op_c;
 
-
     // Memory index involved into a memory operation per pertaining intermediate register
     // We should range constrain it to 32 bits ultimately. For first version of the AVM,
     // we will assume that these columns are of the right type.
     pol commit mem_idx_a;
     pol commit mem_idx_b;
     pol commit mem_idx_c;
-
 
     // Track the last line of the execution trace. It does NOT correspond to the last row of the whole table
     // of size N. As this depends on the supplied bytecode, this polynomial cannot be constant.
     pol commit last;
 
     // Relations on type constraints
-
+    // TODO: Very likely, we can remove these constraints as the selectors should be derived during
+    // opcode decomposition.
     sel_op_add * (1 - sel_op_add) = 0;
     sel_op_sub * (1 - sel_op_sub) = 0;
     sel_op_mul * (1 - sel_op_mul) = 0;
@@ -121,6 +123,7 @@ namespace avm_main(256);
     sel_op_and * (1 - sel_op_and) = 0;
     sel_op_or * (1 - sel_op_or) = 0;
     sel_op_xor * (1 - sel_op_xor) = 0;
+    sel_op_cast * (1 - sel_op_cast) = 0;
 
     sel_internal_call * (1 - sel_internal_call) = 0;
     sel_internal_return * (1 - sel_internal_return) = 0;
@@ -226,7 +229,8 @@ namespace avm_main(256);
 
     //===== CONTROL_FLOW_CONSISTENCY ============================================
     pol INTERNAL_CALL_STACK_SELECTORS = (first + sel_internal_call + sel_internal_return + sel_halt);
-    pol OPCODE_SELECTORS = (sel_op_add + sel_op_sub + sel_op_div + sel_op_mul + sel_op_not + sel_op_eq + sel_op_and + sel_op_or + sel_op_xor);
+    pol OPCODE_SELECTORS = (sel_op_add + sel_op_sub + sel_op_div + sel_op_mul + sel_op_not
+                          + sel_op_eq + sel_op_and + sel_op_or + sel_op_xor + sel_op_cast);
 
     // Program counter must increment if not jumping or returning
     #[PC_INCREMENT]
@@ -244,25 +248,33 @@ namespace avm_main(256);
     #[MOV_MAIN_SAME_TAG]
     sel_mov * (r_in_tag - w_in_tag) = 0;
 
+    //===== ALU CONSTRAINTS =====================================================
+    // TODO: when division is moved to the alu, we will need to add the selector in the list below.
+    pol ALU_R_TAG_SEL = sel_op_add + sel_op_sub + sel_op_mul + sel_op_not + sel_op_eq;
+    pol ALU_W_TAG_SEL = sel_op_cast;
+    pol ALU_ALL_SEL = ALU_R_TAG_SEL + ALU_W_TAG_SEL;
+
+    // Predicate to activate the copy of intermediate registers to ALU table. If tag_err == 1,
+    // the operation is not copied to the ALU table.
+    alu_sel = ALU_ALL_SEL * (1 - tag_err);
+
+    // Dispatch the correct in_tag for alu
+    ALU_R_TAG_SEL * (alu_in_tag - r_in_tag) = 0;
+    ALU_W_TAG_SEL * (alu_in_tag - w_in_tag) = 0;
+
     //====== Inter-table Constraints ============================================
     #[INCL_MAIN_TAG_ERR]
     avm_mem.tag_err {avm_mem.clk} in tag_err {clk};
 
     #[INCL_MEM_TAG_ERR]
     tag_err {clk} in avm_mem.tag_err {avm_mem.clk};
 
-    // Predicate to activate the copy of intermediate registers to ALU table. If tag_err == 1,
-    // the operation is not copied to the ALU table.
-    // TODO: when division is moved to the alu, we will need to add the selector in the list below:
-    alu_sel = (sel_op_add + sel_op_sub + sel_op_mul + sel_op_not + sel_op_eq) * (1 - tag_err);
-
     #[PERM_MAIN_ALU]
     alu_sel {clk, ia, ib, ic, sel_op_add, sel_op_sub,
-             sel_op_mul, sel_op_eq, sel_op_not, r_in_tag}
+             sel_op_mul, sel_op_eq, sel_op_not, alu_in_tag}
     is
     avm_alu.alu_sel {avm_alu.clk, avm_alu.ia, avm_alu.ib, avm_alu.ic, avm_alu.op_add, avm_alu.op_sub,
                      avm_alu.op_mul, avm_alu.op_eq, avm_alu.op_not, avm_alu.in_tag};
-
     // Based on the boolean selectors, we derive the binary op id to lookup in the table;
     // TODO: Check if having 4 columns (op_id + 3 boolean selectors) is more optimal that just using the op_id
     // but with a higher degree constraint: op_id * (op_id - 1) * (op_id - 2)