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sys_prime_map.map
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Release 14.7 Map P.20131013 (nt)
Xilinx Map Application Log File for Design 'sys_prime'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s200a-vq100-4 -cm area -ir off -pr off
-c 100 -o sys_prime_map.ncd sys_prime.ngd sys_prime.pcf
Target Device : xc3s200a
Target Package : vq100
Target Speed : -4
Mapper Version : spartan3a -- $Revision: 1.55 $
Mapped Date : Tue Apr 03 00:19:13 2018
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
WARNING:PhysDesignRules:372 - Gated clock. Clock net ss/clock_ss is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Number of Slice Flip Flops: 675 out of 3,584 18%
Number of 4 input LUTs: 2,313 out of 3,584 64%
Logic Distribution:
Number of occupied Slices: 1,389 out of 1,792 77%
Number of Slices containing only related logic: 1,389 out of 1,389 100%
Number of Slices containing unrelated logic: 0 out of 1,389 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 2,351 out of 3,584 65%
Number used as logic: 2,313
Number used as a route-thru: 38
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 38 out of 68 55%
Number of BUFGMUXs: 4 out of 24 16%
Average Fanout of Non-Clock Nets: 3.65
Peak Memory Usage: 315 MB
Total REAL time to MAP completion: 6 secs
Total CPU time to MAP completion: 5 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "sys_prime_map.mrp" for details.