STM32 I2S Driver Clock Configuration

[erwango]

Discussed in #77480

^{Originally posted by rriveramcrus August 23, 2024}

	if (cfg->pclk_len > 1) {
		if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
					   (clock_control_subsys_t)&cfg->pclken[1],
					   &freq_in) < 0) {
			LOG_ERR("Failed call clock_control_get_rate(pclken[1])");
			return -EIO;
		}
	}
	/*
	 * The ratio between input clock (I2SxClk) and output
	 * clock on the pad (I2S_CK) is obtained using the
	 * following formula:
	 *   (i2s_div * 2) + i2s_odd
	 */
	i2s_div = div_round_closest(freq_in, bit_clk_freq);
	i2s_odd = (i2s_div & 0x1) ? 1 : 0;
	i2s_div >>= 1;

Hello, I am a bit confused by this code snippet in the i2s_ll_stm32.c driver. This snippet comes from the i2s_stm32_set_clock function. I don't expect pclk_len to ever be greater than 1, so freq_in is never set. Am I missing something in my understanding of the I2S and clocking drivers?

For context I am trying to run the i2s output sample application on an STM32 Nucelo F401RE to verify a sine wave output. My overlay and clock configuration are here: 8c9c638

[erwango]

Fixed by #77655, but V3.70 backport PR expects an issue.