Skip to content

Commit e6f5ad3

Browse files
aiamadeusaiamadeus
committed
rockchip: add kernel 6.1 support
1 parent b4bbdc1 commit e6f5ad3

File tree

71 files changed

+46
-7100
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

71 files changed

+46
-7100
lines changed

‎package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch

+16-41
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
1515
--- /dev/null
1616
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
17-
@@ -0,0 +1,38 @@
17+
@@ -0,0 +1,25 @@
1818
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1919
+#include "rk3328-nanopi-r2s.dts"
2020
+
@@ -23,86 +23,59 @@
2323
+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
2424
+};
2525
+
26-
+&lan_led {
27-
+ label = "orangepi-r1-plus:green:lan";
28-
+};
29-
+
3026
+&spi0 {
3127
+ status = "okay";
3228
+
3329
+ flash@0 {
3430
+ compatible = "jedec,spi-nor";
3531
+ reg = <0>;
36-
+ spi-max-frequency = <10000000>;
32+
+ spi-max-frequency = <50000000>;
3733
+ };
3834
+};
3935
+
4036
+&sys_led {
4137
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
42-
+ label = "orangepi-r1-plus:red:sys";
4338
+};
4439
+
4540
+&sys_led_pin {
4641
+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
4742
+};
48-
+
49-
+&uart1 {
50-
+ status = "okay";
51-
+};
52-
+
53-
+&wan_led {
54-
+ label = "orangepi-r1-plus:green:wan";
55-
+};
56-
--- a/board/rockchip/evb_rk3328/MAINTAINERS
57-
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
58-
@@ -12,6 +12,13 @@ F: configs/nanopi-r2s-rk3328_defconfig
59-
F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
60-
F: arch/arm/dts/rk3328-nanopi-r2s.dts
61-
62-
+ORANGEPI-R1-PLUS-RK3328
63-
+M: Shenzhen Xunlong Software CO.,Limited <[email protected]>
64-
+S: Maintained
65-
+F: configs/orangepi-r1-plus-rk3328_defconfig
66-
+F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
67-
+F: arch/arm/dts/rk3328-orangepi-r1-plus.dts
68-
+
69-
ROC-RK3328-CC
70-
M: Loic Devulder <[email protected]>
71-
M: Chen-Yu Tsai <[email protected]>
7243
--- /dev/null
7344
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
74-
@@ -0,0 +1,100 @@
45+
@@ -0,0 +1,104 @@
7546
+CONFIG_ARM=y
47+
+CONFIG_SKIP_LOWLEVEL_INIT=y
48+
+CONFIG_COUNTER_FREQUENCY=24000000
7649
+CONFIG_ARCH_ROCKCHIP=y
7750
+CONFIG_SYS_TEXT_BASE=0x00200000
78-
+CONFIG_SPL_GPIO_SUPPORT=y
51+
+CONFIG_SPL_GPIO=y
52+
+CONFIG_NR_DRAM_BANKS=1
7953
+CONFIG_ENV_OFFSET=0x3F8000
54+
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
8055
+CONFIG_ROCKCHIP_RK3328=y
8156
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
8257
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
8358
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
84-
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
59+
+CONFIG_SPL_DRIVERS_MISC=y
8560
+CONFIG_SPL_STACK_R_ADDR=0x600000
86-
+CONFIG_NR_DRAM_BANKS=1
87-
+CONFIG_SYS_LOAD_ADDR=0x800800
8861
+CONFIG_DEBUG_UART_BASE=0xFF130000
8962
+CONFIG_DEBUG_UART_CLOCK=24000000
90-
+CONFIG_SYSINFO=y
63+
+CONFIG_SYS_LOAD_ADDR=0x800800
9164
+CONFIG_DEBUG_UART=y
9265
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
9366
+# CONFIG_ANDROID_BOOT_IMAGE is not set
9467
+CONFIG_FIT=y
9568
+CONFIG_FIT_VERBOSE=y
9669
+CONFIG_SPL_LOAD_FIT=y
9770
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
98-
+CONFIG_MISC_INIT_R=y
9971
+# CONFIG_DISPLAY_CPUINFO is not set
10072
+CONFIG_DISPLAY_BOARDINFO_LATE=y
73+
+CONFIG_MISC_INIT_R=y
10174
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
10275
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
10376
+CONFIG_SPL_STACK_R=y
104-
+CONFIG_SPL_I2C_SUPPORT=y
105-
+CONFIG_SPL_POWER_SUPPORT=y
77+
+CONFIG_SPL_I2C=y
78+
+CONFIG_SPL_POWER=y
10679
+CONFIG_SPL_ATF=y
10780
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
10881
+CONFIG_CMD_BOOTZ=y
@@ -113,11 +86,11 @@
11386
+CONFIG_CMD_TIME=y
11487
+CONFIG_SPL_OF_CONTROL=y
11588
+CONFIG_TPL_OF_CONTROL=y
116-
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
11789
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
11890
+CONFIG_TPL_OF_PLATDATA=y
11991
+CONFIG_ENV_IS_IN_MMC=y
12092
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
93+
+CONFIG_SYS_MMC_ENV_DEV=1
12194
+CONFIG_NET_RANDOM_ETHADDR=y
12295
+CONFIG_TPL_DM=y
12396
+CONFIG_REGMAP=y
@@ -142,6 +115,7 @@
142115
+CONFIG_SPL_PINCTRL=y
143116
+CONFIG_DM_PMIC=y
144117
+CONFIG_PMIC_RK8XX=y
118+
+CONFIG_SPL_PMIC_RK8XX=y
145119
+CONFIG_SPL_DM_REGULATOR=y
146120
+CONFIG_REGULATOR_PWM=y
147121
+CONFIG_DM_REGULATOR_FIXED=y
@@ -154,6 +128,7 @@
154128
+CONFIG_DM_RESET=y
155129
+CONFIG_BAUDRATE=1500000
156130
+CONFIG_DEBUG_UART_SHIFT=2
131+
+CONFIG_SYSINFO=y
157132
+CONFIG_SYSRESET=y
158133
+# CONFIG_TPL_SYSRESET is not set
159134
+CONFIG_USB=y

‎package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch

+17-17
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,6 @@ Subject: [PATCH] Add support for Orangepi R1 Plus LTS
1111
create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
1212
create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
1313

14-
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
15-
index adfe6c3f..3d4e0f59 100644
1614
--- a/arch/arm/dts/Makefile
1715
+++ b/arch/arm/dts/Makefile
1816
@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
@@ -23,9 +21,10 @@ index adfe6c3f..3d4e0f59 100644
2321
rk3328-roc-cc.dtb \
2422
rk3328-rock64.dtb \
2523
rk3328-rock-pi-e.dtb
26-
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
27-
new file mode 100644
28-
index 00000000..e6225b0c
24+
--- /dev/null
25+
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
26+
@@ -0,0 +1,1 @@
27+
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
2928
--- /dev/null
3029
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
3130
@@ -0,0 +1,7 @@
@@ -36,27 +35,26 @@ index 00000000..e6225b0c
3635
+ model = "Xunlong Orange Pi R1 Plus LTS";
3736
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
3837
+};
39-
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
40-
new file mode 100644
41-
index 00000000..3cb3b5c3
4238
--- /dev/null
4339
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
44-
@@ -0,0 +1,100 @@
40+
@@ -0,0 +1,104 @@
4541
+CONFIG_ARM=y
42+
+CONFIG_SKIP_LOWLEVEL_INIT=y
43+
+CONFIG_COUNTER_FREQUENCY=24000000
4644
+CONFIG_ARCH_ROCKCHIP=y
4745
+CONFIG_SYS_TEXT_BASE=0x00200000
48-
+CONFIG_SPL_GPIO_SUPPORT=y
46+
+CONFIG_SPL_GPIO=y
47+
+CONFIG_NR_DRAM_BANKS=1
4948
+CONFIG_ENV_OFFSET=0x3F8000
49+
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
5050
+CONFIG_ROCKCHIP_RK3328=y
5151
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
5252
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
5353
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
54-
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
54+
+CONFIG_SPL_DRIVERS_MISC=y
5555
+CONFIG_SPL_STACK_R_ADDR=0x600000
56-
+CONFIG_NR_DRAM_BANKS=1
5756
+CONFIG_DEBUG_UART_BASE=0xFF130000
5857
+CONFIG_DEBUG_UART_CLOCK=24000000
59-
+CONFIG_SYSINFO=y
6058
+CONFIG_SYS_LOAD_ADDR=0x800800
6159
+CONFIG_DEBUG_UART=y
6260
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
@@ -65,14 +63,14 @@ index 00000000..3cb3b5c3
6563
+CONFIG_FIT_VERBOSE=y
6664
+CONFIG_SPL_LOAD_FIT=y
6765
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
68-
+CONFIG_MISC_INIT_R=y
6966
+# CONFIG_DISPLAY_CPUINFO is not set
7067
+CONFIG_DISPLAY_BOARDINFO_LATE=y
68+
+CONFIG_MISC_INIT_R=y
7169
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
7270
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
7371
+CONFIG_SPL_STACK_R=y
74-
+CONFIG_SPL_I2C_SUPPORT=y
75-
+CONFIG_SPL_POWER_SUPPORT=y
72+
+CONFIG_SPL_I2C=y
73+
+CONFIG_SPL_POWER=y
7674
+CONFIG_SPL_ATF=y
7775
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
7876
+CONFIG_CMD_BOOTZ=y
@@ -83,11 +81,11 @@ index 00000000..3cb3b5c3
8381
+CONFIG_CMD_TIME=y
8482
+CONFIG_SPL_OF_CONTROL=y
8583
+CONFIG_TPL_OF_CONTROL=y
86-
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
8784
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
8885
+CONFIG_TPL_OF_PLATDATA=y
8986
+CONFIG_ENV_IS_IN_MMC=y
9087
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
88+
+CONFIG_SYS_MMC_ENV_DEV=1
9189
+CONFIG_NET_RANDOM_ETHADDR=y
9290
+CONFIG_TPL_DM=y
9391
+CONFIG_REGMAP=y
@@ -112,6 +110,7 @@ index 00000000..3cb3b5c3
112110
+CONFIG_SPL_PINCTRL=y
113111
+CONFIG_DM_PMIC=y
114112
+CONFIG_PMIC_RK8XX=y
113+
+CONFIG_SPL_PMIC_RK8XX=y
115114
+CONFIG_SPL_DM_REGULATOR=y
116115
+CONFIG_REGULATOR_PWM=y
117116
+CONFIG_DM_REGULATOR_FIXED=y
@@ -124,6 +123,7 @@ index 00000000..3cb3b5c3
124123
+CONFIG_DM_RESET=y
125124
+CONFIG_BAUDRATE=1500000
126125
+CONFIG_DEBUG_UART_SHIFT=2
126+
+CONFIG_SYSINFO=y
127127
+CONFIG_SYSRESET=y
128128
+# CONFIG_TPL_SYSRESET is not set
129129
+CONFIG_USB=y

‎target/linux/rockchip/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-pa
88
SUBTARGETS:=armv8
99

1010
KERNEL_PATCHVER:=5.15
11-
KERNEL_TESTING_PATCHVER:=6.0
11+
KERNEL_TESTING_PATCHVER:=6.1
1212

1313
define Target/Description
1414
Build firmware image for Rockchip SoC devices.

‎target/linux/rockchip/armv8/config-6.0 ‎target/linux/rockchip/armv8/config-6.1

+3-16
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ CONFIG_ARM64_ERRATUM_832075=y
3030
CONFIG_ARM64_ERRATUM_843419=y
3131
CONFIG_ARM64_ERRATUM_845719=y
3232
CONFIG_ARM64_ERRATUM_858921=y
33+
CONFIG_ARM64_ERRATUM_1742098=y
3334
CONFIG_ARM64_HW_AFDBM=y
3435
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
3536
CONFIG_ARM64_MODULE_PLTS=y
@@ -168,32 +169,17 @@ CONFIG_CRYPTO_AES_ARM64=y
168169
CONFIG_CRYPTO_AES_ARM64_CE=y
169170
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
170171
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
171-
CONFIG_CRYPTO_CBC=y
172172
CONFIG_CRYPTO_CRC32=y
173173
CONFIG_CRYPTO_CRC32C=y
174174
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
175175
CONFIG_CRYPTO_CRCT10DIF=y
176176
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
177177
CONFIG_CRYPTO_CRYPTD=y
178-
CONFIG_CRYPTO_DES=y
179-
CONFIG_CRYPTO_DEV_ROCKCHIP=y
180-
CONFIG_CRYPTO_DEV_ROCKCHIP2=y
181-
# CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set
182-
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
183-
CONFIG_CRYPTO_ECB=y
184-
CONFIG_CRYPTO_ENGINE=y
185178
CONFIG_CRYPTO_GHASH_ARM64_CE=y
186-
CONFIG_CRYPTO_HW=y
187-
CONFIG_CRYPTO_LIB_DES=y
188179
CONFIG_CRYPTO_LIB_SHA1=y
189180
CONFIG_CRYPTO_LIB_SHA256=y
190-
CONFIG_CRYPTO_MD5=y
191181
CONFIG_CRYPTO_NULL2=y
192182
CONFIG_CRYPTO_RNG2=y
193-
CONFIG_CRYPTO_SHA1=y
194-
CONFIG_CRYPTO_SHA512=y
195-
CONFIG_CRYPTO_SM3=y
196-
CONFIG_CRYPTO_SM3_GENERIC=y
197183
CONFIG_CRYPTO_SIMD=y
198184
CONFIG_DCACHE_WORD_ACCESS=y
199185
CONFIG_DEBUG_BUGVERBOSE=y
@@ -222,6 +208,7 @@ CONFIG_DUMMY_CONSOLE=y
222208
CONFIG_DWMAC_DWC_QOS_ETH=y
223209
CONFIG_DWMAC_GENERIC=y
224210
CONFIG_DWMAC_ROCKCHIP=y
211+
CONFIG_DW_WATCHDOG=y
225212
CONFIG_EDAC_SUPPORT=y
226213
CONFIG_EEPROM_AT24=y
227214
CONFIG_EMAC_ROCKCHIP=y
@@ -696,7 +683,7 @@ CONFIG_VM_EVENT_COUNTERS=y
696683
CONFIG_VT=y
697684
CONFIG_VT_CONSOLE=y
698685
CONFIG_VT_HW_CONSOLE_BINDING=y
699-
# CONFIG_WATCHDOG is not set
686+
CONFIG_WATCHDOG_CORE=y
700687
CONFIG_XARRAY_MULTI=y
701688
CONFIG_XPS=y
702689
CONFIG_XXHASH=y

‎target/linux/rockchip/image/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ define Device/Default
7373
DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1)))
7474
endef
7575

76-
ifdef CONFIG_LINUX_6_0
76+
ifdef CONFIG_LINUX_6_1
7777
DTS_CPPFLAGS += -DDTS_NO_LEGACY
7878
endif
7979

0 commit comments

Comments
 (0)