diff --git a/cranelift/codegen/src/isa/aarch64/lower.isle b/cranelift/codegen/src/isa/aarch64/lower.isle
index 6e1739adcb0c..6d5cc87f9201 100644
--- a/cranelift/codegen/src/isa/aarch64/lower.isle
+++ b/cranelift/codegen/src/isa/aarch64/lower.isle
@@ -107,6 +107,20 @@
 (rule (lower (has_type vec_i128_ty (swizzle rn rm)))
       (vec_tbl rn rm #f))
 
+;;;; Rules for `isplit` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type $I64 (isplit x)))
+      (let
+          ((x_regs ValueRegs x)
+           (x_lo ValueRegs (value_regs_get x_regs 0))
+           (x_hi ValueRegs (value_regs_get x_regs 1)))
+        (output_pair x_lo x_hi)))
+
+;;;; Rules for `iconcat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type $I128 (iconcat lo hi)))
+      (output (value_regs lo hi)))
+
 ;;;; Rules for `iadd_pairwise` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (has_type $I16X8 (iadd_pairwise (swiden_low x) (swiden_high y))))
diff --git a/cranelift/codegen/src/isa/aarch64/lower_inst.rs b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
index 5a5f2c0a992a..b407ef3dd92a 100644
--- a/cranelift/codegen/src/isa/aarch64/lower_inst.rs
+++ b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
@@ -1212,47 +1212,9 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
 
         Opcode::Swizzle => implemented_in_isle(ctx),
 
-        Opcode::Isplit => {
-            let input_ty = ctx.input_ty(insn, 0);
-
-            if input_ty != I128 {
-                return Err(CodegenError::Unsupported(format!(
-                    "Isplit: Unsupported type: {:?}",
-                    input_ty
-                )));
-            }
+        Opcode::Isplit => implemented_in_isle(ctx),
 
-            assert_eq!(ctx.output_ty(insn, 0), I64);
-            assert_eq!(ctx.output_ty(insn, 1), I64);
-
-            let src_regs = put_input_in_regs(ctx, inputs[0]);
-            let dst_lo = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let dst_hi = get_output_reg(ctx, outputs[1]).only_reg().unwrap();
-
-            ctx.emit(Inst::gen_move(dst_lo, src_regs.regs()[0], I64));
-            ctx.emit(Inst::gen_move(dst_hi, src_regs.regs()[1], I64));
-        }
-
-        Opcode::Iconcat => {
-            let ty = ty.unwrap();
-
-            if ty != I128 {
-                return Err(CodegenError::Unsupported(format!(
-                    "Iconcat: Unsupported type: {:?}",
-                    ty
-                )));
-            }
-
-            assert_eq!(ctx.input_ty(insn, 0), I64);
-            assert_eq!(ctx.input_ty(insn, 1), I64);
-
-            let src_lo = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let src_hi = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let dst = get_output_reg(ctx, outputs[0]);
-
-            ctx.emit(Inst::gen_move(dst.regs()[0], src_lo, I64));
-            ctx.emit(Inst::gen_move(dst.regs()[1], src_hi, I64));
-        }
+        Opcode::Iconcat => implemented_in_isle(ctx),
 
         Opcode::Imax | Opcode::Umax | Opcode::Umin | Opcode::Imin => implemented_in_isle(ctx),
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/call.clif b/cranelift/filetests/filetests/isa/aarch64/call.clif
index 41ed9a3e9d50..597266f79cb8 100644
--- a/cranelift/filetests/filetests/isa/aarch64/call.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/call.clif
@@ -317,12 +317,12 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   mov x9, x0
+;   mov x7, x0
 ;   movz x0, #42
-;   mov x1, x9
+;   mov x1, x7
 ;   movz x2, #42
-;   ldr x14, 8 ; b 12 ; data TestCase { length: 3, ascii: [102, 49, 49, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] } + 0
-;   blr x14
+;   ldr x10, 8 ; b 12 ; data TestCase { length: 3, ascii: [102, 49, 49, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] } + 0
+;   blr x10
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -349,11 +349,12 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
+;   mov x7, x0
 ;   movz x3, #42
-;   mov x2, x0
 ;   movz x0, #42
-;   ldr x14, 8 ; b 12 ; data TestCase { length: 3, ascii: [102, 49, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] } + 0
-;   blr x14
+;   mov x2, x7
+;   ldr x10, 8 ; b 12 ; data TestCase { length: 3, ascii: [102, 49, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] } + 0
+;   blr x10
 ;   ldp fp, lr, [sp], #16
 ;   ret
 
@@ -380,11 +381,12 @@ block0(v0: i64):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
+;   mov x7, x0
 ;   movz x2, #42
-;   mov x1, x0
 ;   movz x0, #42
-;   ldr x14, 8 ; b 12 ; data TestCase { length: 3, ascii: [102, 49, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] } + 0
-;   blr x14
+;   mov x1, x7
+;   ldr x10, 8 ; b 12 ; data TestCase { length: 3, ascii: [102, 49, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] } + 0
+;   blr x10
 ;   ldp fp, lr, [sp], #16
 ;   ret