[Feature] AXI-Stream support

[iDoka]

I'm very happy to appear great substitute proprietary IP for debugging inside real HW (like Xilinx JTAG-to-AXI).

I think would be great to have option to stream RAW data to/from host, AXI-Stream support is suitable way to this case.
Here I mean either support AXI-MM (MemMap) or AXI-Stream at the same runtime (for reason stay core simple).

[ultraembedded]

I missed the notification on this one. I do have a version which has what you are asking for. I’ll look into releasing it this weekend.

[iDoka]

Sounds great!

Host-to-FPGA AXI stream transfer almost the same as AXI MM in BURST mode

Please allow me to share some trivial ideas for FPGA-to-Host implementation on FPGA side:

1. Should to have limitation for AXI-stream "packet" size (for FPGA user logic, see next point)
2. FPGA-to-Host using TLAST (from user logic) to "slicing" stream to packets with predefined size (user logic should proper issue TLAST signal according to such size)
3. Size should be choice with reasonable way (correlation with FIFO size in FTDI/FPGA part)
4. Choice size from predefined range by user on synthesis stage is desirable to play throughput/latence tradeoff

[cairo-caplan]

Hello @ultraembedded,

I would like to know if you have made available a streamed version of your core. Also, do you have a documentation available on how to integrate or use the current one?

Kind regards,

[GaLaKtIkUs]

Hi @ultraembedded,
Any updates on this?

[cairo-caplan]

Hi @ultraembedded,
Any updates on this?

I ended up doing my own based on the FTDI Bus Master example project, but using Intel's Avalon Stream interfaces.