From 3c4253aef0f65ec55af83355a51a8b427bd6ea0a Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 10 Oct 2022 16:18:43 -0700 Subject: [PATCH] Update CounterFile.scala --- src/main/scala/gemmini/CounterFile.scala | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/main/scala/gemmini/CounterFile.scala b/src/main/scala/gemmini/CounterFile.scala index 35f50c20..7b28b8e2 100644 --- a/src/main/scala/gemmini/CounterFile.scala +++ b/src/main/scala/gemmini/CounterFile.scala @@ -225,8 +225,8 @@ class CounterController(nPerfCounter: Int, counterWidth: Int)(implicit p: Parame if (nPerfCounter > 0) { val nCounterIndexBit = log2Ceil(nPerfCounter) - val module = Module(new CounterFile(nPerfCounter: Int, counterWidth: Int)) - module.io.event_io <> io.event_io + val counterfile = Module(new CounterFile(nPerfCounter: Int, counterWidth: Int)) + counterfile.io.event_io <> io.event_io val out_reg = Reg(io.out.bits.cloneType) val out_valid_reg = RegInit(false.B) @@ -242,13 +242,13 @@ class CounterController(nPerfCounter: Int, counterWidth: Int)(implicit p: Parame // rs1[31] = External counter flag io.in.ready := !out_valid_reg - module.io.addr := io.in.bits.rs1(nCounterIndexBit + 3, 4) - module.io.counter_reset := io.in.bits.rs1(0) & io.in.fire - module.io.snapshot_reset := io.in.bits.rs1(1) & io.in.fire - module.io.snapshot := io.in.bits.rs1(2) & io.in.fire - module.io.config_address.valid := io.in.bits.rs1(3) & io.in.fire - module.io.config_address.bits := io.in.bits.rs1(17, 12) - module.io.external := io.in.bits.rs1(31) + counterfile.io.addr := io.in.bits.rs1(nCounterIndexBit + 3, 4) + counterfile.io.counter_reset := io.in.bits.rs1(0) & io.in.fire + counterfile.io.snapshot_reset := io.in.bits.rs1(1) & io.in.fire + counterfile.io.snapshot := io.in.bits.rs1(2) & io.in.fire + counterfile.io.config_address.valid := io.in.bits.rs1(3) & io.in.fire + counterfile.io.config_address.bits := io.in.bits.rs1(17, 12) + counterfile.io.external := io.in.bits.rs1(31) when (io.out.fire) { out_valid_reg := false.B @@ -256,7 +256,7 @@ class CounterController(nPerfCounter: Int, counterWidth: Int)(implicit p: Parame out_valid_reg := true.B out_reg.rd := io.in.bits.inst.rd out_reg.data := 0.U - out_reg.data := module.io.data + out_reg.data := counterfile.io.data } io.out.valid := out_valid_reg