diff --git a/src/main/scala/firrtl2/AddDescriptionNodes.scala b/src/main/scala/firrtl2/AddDescriptionNodes.scala index e3e78e86a..a4bec8265 100644 --- a/src/main/scala/firrtl2/AddDescriptionNodes.scala +++ b/src/main/scala/firrtl2/AddDescriptionNodes.scala @@ -153,7 +153,6 @@ class AddDescriptionNodes extends Transform with DependencyAPIMigration { Dependency[firrtl2.transforms.InlineAcrossCastsTransform], Dependency[firrtl2.transforms.LegalizeClocksAndAsyncResetsTransform], Dependency[firrtl2.transforms.FlattenRegUpdate], - Dependency(passes.VerilogModulusCleanup), Dependency[firrtl2.transforms.VerilogRename], Dependency(firrtl2.passes.VerilogPrep) ) diff --git a/src/main/scala/firrtl2/LoweringCompilers.scala b/src/main/scala/firrtl2/LoweringCompilers.scala index e5570619a..97b46e1c0 100644 --- a/src/main/scala/firrtl2/LoweringCompilers.scala +++ b/src/main/scala/firrtl2/LoweringCompilers.scala @@ -2,7 +2,6 @@ package firrtl2 -import firrtl2.transforms.IdentityTransform import firrtl2.stage.{Forms, TransformManager} @deprecated("Use a TransformManager or some other Stage/Phase class. Will be removed in 1.4.", "FIRRTL 1.2") @@ -105,19 +104,6 @@ class MinimumLowFirrtlOptimization extends CoreTransform { def transforms = new TransformManager(Forms.LowFormMinimumOptimized, Forms.LowForm).flattenedTransformOrder } -/** Emits input circuit with no changes - * - * Primarily useful for changing between .fir and .pb serialized formats - */ -@deprecated( - "Use stage.{FirrtlStage, FirrtlMain} or stage.transforms.Compiler(Seq(Dependency[ChirrtlEmitter]))", - "FIRRTL 1.3" -) -class NoneCompiler extends Compiler { - val emitter = new ChirrtlEmitter - def transforms: Seq[Transform] = Seq(new IdentityTransform(ChirrtlForm)) -} - /** Emits input circuit * Will replace Chirrtl constructs with Firrtl */ diff --git a/src/main/scala/firrtl2/options/phases/ConvertLegacyAnnotations.scala b/src/main/scala/firrtl2/options/phases/ConvertLegacyAnnotations.scala deleted file mode 100644 index 2859fdd17..000000000 --- a/src/main/scala/firrtl2/options/phases/ConvertLegacyAnnotations.scala +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package firrtl2.options.phases - -import firrtl2.AnnotationSeq -import firrtl2.options.{Dependency, Phase} - -@deprecated("LegacyAnnotation has been removed, this is a no-op", "FIRRTL 1.4") -class ConvertLegacyAnnotations extends Phase { - - override def prerequisites = Seq(Dependency[GetIncludes]) - - override def optionalPrerequisiteOf = Seq.empty - - override def invalidates(a: Phase) = false - - def transform(annotations: AnnotationSeq): AnnotationSeq = annotations -} diff --git a/src/main/scala/firrtl2/passes/ToWorkingIR.scala b/src/main/scala/firrtl2/passes/ToWorkingIR.scala deleted file mode 100644 index b21f3b853..000000000 --- a/src/main/scala/firrtl2/passes/ToWorkingIR.scala +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package firrtl2.passes - -import firrtl2.ir._ -import firrtl2.Transform - -@deprecated( - "This pass is an identity transform. For an equivalent dependency, use firrtl.stage.forms.MinimalHighForm", - "FIRRTL 1.4.2" -) -object ToWorkingIR extends Pass { - override def prerequisites = firrtl2.stage.Forms.MinimalHighForm - override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = - (firrtl2.stage.Forms.LowFormOptimized.toSet -- firrtl2.stage.Forms.MinimalHighForm).toSeq - override def invalidates(a: Transform) = false - def run(c: Circuit): Circuit = c -} diff --git a/src/main/scala/firrtl2/passes/Uniquify.scala b/src/main/scala/firrtl2/passes/Uniquify.scala deleted file mode 100644 index 25d1c8693..000000000 --- a/src/main/scala/firrtl2/passes/Uniquify.scala +++ /dev/null @@ -1,369 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package firrtl2.passes - -import scala.annotation.tailrec -import firrtl2._ -import firrtl2.ir._ -import firrtl2.Utils._ -import firrtl2.Mappers._ -import firrtl2.options.Dependency - -import MemPortUtils.memType - -/** Resolve name collisions that would occur in the old [[LowerTypes]] pass - * - * @note Must be run after [[InferTypes]] because [[ir.DefNode]]s need type - * @example - * {{{ - * wire a = { b, c }[2] - * wire a_0 - * }}} - * This lowers to: - * {{{ - * wire a__0_b - * wire a__0_c - * wire a__1_b - * wire a__1_c - * wire a_0 - * }}} - * There wouldn't be a collision even if we didn't map a -> a_, but - * there WOULD be collisions in references a[0] and a_0 so we still have - * to rename a - */ -@deprecated("Uniquify is now part of LowerTypes", "FIRRTL 1.4.0") -object Uniquify extends Transform with DependencyAPIMigration { - - override def prerequisites = - Seq(Dependency(ResolveKinds), Dependency(InferTypes)) ++ firrtl2.stage.Forms.MinimalHighForm - - override def invalidates(a: Transform): Boolean = a match { - case ResolveKinds | InferTypes => true - case _ => false - } - - private case class UniquifyException(msg: String) extends FirrtlInternalException(msg) - private def error(msg: String)(implicit sinfo: Info, mname: String) = - throw new UniquifyException(s"$sinfo: [moduleOpt $mname] $msg") - - // For creation of rename map - private case class NameMapNode(name: String, elts: Map[String, NameMapNode]) - - /** Appends delim to prefix until no collisions of prefix + elts in names We don't add an _ in the collision check - * because elts could be Seq("") In this case, we're just really checking if prefix itself collides - */ - @deprecated("Use firrtl.Namespace.findValidPrefix", "FIRRTL 1.4.0") - def findValidPrefix( - prefix: String, - elts: Seq[String], - namespace: collection.mutable.HashSet[String] - ): String = Namespace.findValidPrefix(prefix, elts, namespace) - - /** Creates a Bundle Type from a Stmt */ - @deprecated("Use firrtl.Utils.stmtToType", "FIRRTL 1.4.0") - def stmtToType(s: Statement)(implicit sinfo: Info, mname: String): BundleType = - Utils.stmtToType(s) - - // Accepts a Type and an initial namespace - // Returns new Type with uniquified names - private def uniquifyNames( - t: BundleType, - namespace: collection.mutable.HashSet[String] - )( - implicit sinfo: Info, - mname: String - ): BundleType = { - def recUniquifyNames(t: Type, namespace: collection.mutable.HashSet[String]): (Type, Seq[String]) = t match { - case tx: BundleType => - // First add everything - val newFieldsAndElts = tx.fields.map { f => - val newName = Namespace.findValidPrefix(f.name, Seq(""), namespace) - namespace += newName - Field(newName, f.flip, f.tpe) - }.map { f => - f.tpe match { - case _: GroundType => (f, Seq[String](f.name)) - case _ => - val (tpe, eltsx) = recUniquifyNames(f.tpe, collection.mutable.HashSet()) - // Need leading _ for findValidPrefix, it doesn't add _ for checks - val eltsNames: Seq[String] = eltsx.map(e => "_" + e) - val prefix = Namespace.findValidPrefix(f.name, eltsNames, namespace) - // We added f.name in previous map, delete if we change it - if (prefix != f.name) { - namespace -= f.name - namespace += prefix - } - val newElts: Seq[String] = eltsx.map(e => LowerTypes.loweredName(prefix +: Seq(e))) - namespace ++= newElts - (Field(prefix, f.flip, tpe), prefix +: newElts) - } - } - val (newFields, elts) = newFieldsAndElts.unzip - (BundleType(newFields), elts.flatten) - case tx: VectorType => - val (tpe, elts) = recUniquifyNames(tx.tpe, namespace) - val newElts = ((0 until tx.size).map(i => i.toString)) ++ - ((0 until tx.size).flatMap { i => - elts.map(e => LowerTypes.loweredName(Seq(i.toString, e))) - }) - (VectorType(tpe, tx.size), newElts) - case tx => (tx, Nil) - } - val (tpe, _) = recUniquifyNames(t, namespace) - tpe match { - case tx: BundleType => tx - case tx => throwInternalError(s"uniquifyNames: shouldn't be here - $tx") - } - } - - // Creates a mapping from flattened references to members of $from -> - // flattened references to members of $to - private def createNameMapping( - from: Type, - to: Type - )( - implicit sinfo: Info, - mname: String - ): Map[String, NameMapNode] = { - (from, to) match { - case (fromx: BundleType, tox: BundleType) => - (fromx.fields - .zip(tox.fields) - .flatMap { - case (f, t) => - val eltsMap = createNameMapping(f.tpe, t.tpe) - if ((f.name != t.name) || eltsMap.nonEmpty) { - Map(f.name -> NameMapNode(t.name, eltsMap)) - } else { - Map[String, NameMapNode]() - } - }) - .toMap - case (fromx: VectorType, tox: VectorType) => - createNameMapping(fromx.tpe, tox.tpe) - case (fromx, tox) => - if (fromx.getClass == tox.getClass) Map() - else error("Types to map between do not match!") - } - } - - // Maps names in expression to new uniquified names - private def uniquifyNamesExp( - exp: Expression, - map: Map[String, NameMapNode] - )( - implicit sinfo: Info, - mname: String - ): Expression = { - // Recursive Helper - def rec(exp: Expression, m: Map[String, NameMapNode]): (Expression, Map[String, NameMapNode]) = exp match { - case e: WRef => - if (m.contains(e.name)) { - val node = m(e.name) - (WRef(node.name, e.tpe, e.kind, e.flow), node.elts) - } else (e, Map()) - case e: WSubField => - val (subExp, subMap) = rec(e.expr, m) - val (retName, retMap) = - if (subMap.contains(e.name)) { - val node = subMap(e.name) - (node.name, node.elts) - } else { - (e.name, Map[String, NameMapNode]()) - } - (WSubField(subExp, retName, e.tpe, e.flow), retMap) - case e: WSubIndex => - val (subExp, subMap) = rec(e.expr, m) - (WSubIndex(subExp, e.value, e.tpe, e.flow), subMap) - case e: WSubAccess => - val (subExp, subMap) = rec(e.expr, m) - val index = uniquifyNamesExp(e.index, map) - (WSubAccess(subExp, index, e.tpe, e.flow), subMap) - case (_: UIntLiteral | _: SIntLiteral) => (exp, m) - case (_: Mux | _: ValidIf | _: DoPrim) => - (exp.map((e: Expression) => uniquifyNamesExp(e, map)), m) - } - rec(exp, map)._1 - } - - // Uses map to recursively rename fields of tpe - private def uniquifyNamesType( - tpe: Type, - map: Map[String, NameMapNode] - )( - implicit sinfo: Info, - mname: String - ): Type = tpe match { - case t: BundleType => - val newFields = t.fields.map { f => - if (map.contains(f.name)) { - val node = map(f.name) - Field(node.name, f.flip, uniquifyNamesType(f.tpe, node.elts)) - } else { - f - } - } - BundleType(newFields) - case t: VectorType => - VectorType(uniquifyNamesType(t.tpe, map), t.size) - case t => t - } - - // Everything wrapped in run so that it's thread safe - @deprecated( - "The functionality of Uniquify is now part of LowerTypes." + - "Please file an issue with firrtl if you use Uniquify outside of the context of LowerTypes.", - "Firrtl 1.4" - ) - def execute(state: CircuitState): CircuitState = { - val c = state.circuit - val renames = RenameMap() - renames.setCircuit(c.main) - // Debug state - implicit var mname: String = "" - implicit var sinfo: Info = NoInfo - // Global state - val portNameMap = collection.mutable.HashMap[String, Map[String, NameMapNode]]() - val portTypeMap = collection.mutable.HashMap[String, Type]() - - def uniquifyModule(renames: RenameMap)(m: DefModule): DefModule = { - renames.setModule(m.name) - val namespace = collection.mutable.HashSet[String]() - val nameMap = collection.mutable.HashMap[String, NameMapNode]() - - def uniquifyExp(e: Expression): Expression = e match { - case (_: WRef | _: WSubField | _: WSubIndex | _: WSubAccess) => - uniquifyNamesExp(e, nameMap.toMap) - case e: Mux => e.map(uniquifyExp) - case e: ValidIf => e.map(uniquifyExp) - case (_: UIntLiteral | _: SIntLiteral) => e - case e: DoPrim => e.map(uniquifyExp) - } - - def uniquifyStmt(s: Statement): Statement = { - s.map(uniquifyStmt).map(uniquifyExp) match { - case sx: DefWire => - sinfo = sx.info - if (nameMap.contains(sx.name)) { - val node = nameMap(sx.name) - val newType = uniquifyNamesType(sx.tpe, node.elts) - (Utils.create_exps(sx.name, sx.tpe).zip(Utils.create_exps(node.name, newType))).foreach { - case (from, to) => renames.rename(from.serialize, to.serialize) - } - DefWire(sx.info, node.name, newType) - } else { - sx - } - case sx: DefRegister => - sinfo = sx.info - if (nameMap.contains(sx.name)) { - val node = nameMap(sx.name) - val newType = uniquifyNamesType(sx.tpe, node.elts) - (Utils.create_exps(sx.name, sx.tpe).zip(Utils.create_exps(node.name, newType))).foreach { - case (from, to) => renames.rename(from.serialize, to.serialize) - } - DefRegister(sx.info, node.name, newType, sx.clock, sx.reset, sx.init) - } else { - sx - } - case sx: WDefInstance => - sinfo = sx.info - if (nameMap.contains(sx.name)) { - val node = nameMap(sx.name) - val newType = portTypeMap(sx.module) - (Utils.create_exps(sx.name, sx.tpe).zip(Utils.create_exps(node.name, newType))).foreach { - case (from, to) => renames.rename(from.serialize, to.serialize) - } - WDefInstance(sx.info, node.name, sx.module, newType) - } else { - sx - } - case sx: DefMemory => - sinfo = sx.info - if (nameMap.contains(sx.name)) { - val node = nameMap(sx.name) - val dataType = uniquifyNamesType(sx.dataType, node.elts) - val mem = sx.copy(name = node.name, dataType = dataType) - // Create new mapping to handle references to memory data fields - val uniqueMemMap = createNameMapping(memType(sx), memType(mem)) - (Utils.create_exps(sx.name, memType(sx)).zip(Utils.create_exps(node.name, memType(mem)))).foreach { - case (from, to) => renames.rename(from.serialize, to.serialize) - } - nameMap(sx.name) = NameMapNode(node.name, node.elts ++ uniqueMemMap) - mem - } else { - sx - } - case sx: DefNode => - sinfo = sx.info - if (nameMap.contains(sx.name)) { - val node = nameMap(sx.name) - (Utils - .create_exps(sx.name, s.asInstanceOf[DefNode].value.tpe) - .zip(Utils.create_exps(node.name, sx.value.tpe))) - .foreach { - case (from, to) => renames.rename(from.serialize, to.serialize) - } - DefNode(sx.info, node.name, sx.value) - } else { - sx - } - case sx => sx - } - } - - def uniquifyBody(s: Statement): Statement = { - val bodyType = stmtToType(s) - val uniqueBodyType = uniquifyNames(bodyType, namespace) - val localMap = createNameMapping(bodyType, uniqueBodyType) - nameMap ++= localMap - - uniquifyStmt(s) - } - - // uniquify ports and expand aggregate types - sinfo = m.info - mname = m.name - m match { - case m: ExtModule => m - case m: Module => - // Adds port names to namespace and namemap - nameMap ++= portNameMap(m.name) - namespace ++= create_exps("", portTypeMap(m.name)).map(LowerTypes.loweredName).map(_.tail) - m.copy(body = uniquifyBody(m.body)) - } - } - - def uniquifyPorts(renames: RenameMap)(m: DefModule): DefModule = { - renames.setModule(m.name) - def uniquifyPorts(ports: Seq[Port]): Seq[Port] = { - val portsType = BundleType(ports.map { - case Port(_, name, dir, tpe) => Field(name, to_flip(dir), tpe) - }) - val uniquePortsType = uniquifyNames(portsType, collection.mutable.HashSet()) - val localMap = createNameMapping(portsType, uniquePortsType) - portNameMap += (m.name -> localMap) - portTypeMap += (m.name -> uniquePortsType) - - ports.zip(uniquePortsType.fields).map { - case (p, f) => - (Utils.create_exps(p.name, p.tpe).zip(Utils.create_exps(f.name, f.tpe))).foreach { - case (from, to) => renames.rename(from.serialize, to.serialize) - } - Port(p.info, f.name, p.direction, f.tpe) - } - } - - sinfo = m.info - mname = m.name - m match { - case m: ExtModule => m.copy(ports = uniquifyPorts(m.ports)) - case m: Module => m.copy(ports = uniquifyPorts(m.ports)) - } - } - - sinfo = c.info - val result = Circuit(c.info, c.modules.map(uniquifyPorts(renames)).map(uniquifyModule(renames)), c.main) - state.copy(circuit = result, renames = Some(renames)) - } -} diff --git a/src/main/scala/firrtl2/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl2/passes/VerilogModulusCleanup.scala deleted file mode 100644 index 1f1ef42fd..000000000 --- a/src/main/scala/firrtl2/passes/VerilogModulusCleanup.scala +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package firrtl2 -package passes - -import firrtl2.ir._ -import firrtl2.options.Dependency - -import scala.collection.mutable - -/** - * Verilog has the width of (a % b) = Max(W(a), W(b)) - * FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, - * but nevertheless is a problem when emitting verilog - * - * This pass finds every instance of (a % b) and: - * 1) adds a temporary node equal to (a % b) with width Max(W(a), W(b)) - * 2) replaces the reference to (a % b) with a bitslice of the temporary node - * to get back down to width Min(W(a), W(b)) - * - * This is technically incorrect firrtl, but allows the verilog emitter - * to emit correct verilog without needing to add temporary nodes - */ -@deprecated("This pass's functionality has been moved to LegalizeVerilog", "FIRRTL 1.5.2") -object VerilogModulusCleanup extends Pass { - - override def prerequisites = firrtl2.stage.Forms.LowFormMinimumOptimized ++ - Seq( - Dependency[firrtl2.transforms.BlackBoxSourceHelper], - Dependency[firrtl2.transforms.FixAddingNegativeLiterals], - Dependency[firrtl2.transforms.ReplaceTruncatingArithmetic], - Dependency[firrtl2.transforms.InlineBitExtractionsTransform], - Dependency[firrtl2.transforms.InlineAcrossCastsTransform], - Dependency[firrtl2.transforms.LegalizeClocksAndAsyncResetsTransform], - Dependency[firrtl2.transforms.FlattenRegUpdate] - ) - - override def optionalPrerequisites = firrtl2.stage.Forms.LowFormOptimized - - override def optionalPrerequisiteOf = Seq.empty - - override def invalidates(a: Transform) = false - - def run(c: Circuit): Circuit = c -} diff --git a/src/main/scala/firrtl2/passes/VerilogPrep.scala b/src/main/scala/firrtl2/passes/VerilogPrep.scala index bb10d10b0..f0b18e681 100644 --- a/src/main/scala/firrtl2/passes/VerilogPrep.scala +++ b/src/main/scala/firrtl2/passes/VerilogPrep.scala @@ -31,7 +31,6 @@ object VerilogPrep extends Pass { Dependency[firrtl2.transforms.InlineAcrossCastsTransform], Dependency[firrtl2.transforms.LegalizeClocksAndAsyncResetsTransform], Dependency[firrtl2.transforms.FlattenRegUpdate], - Dependency(passes.VerilogModulusCleanup), Dependency[firrtl2.transforms.VerilogRename] ) diff --git a/src/main/scala/firrtl2/stage/Forms.scala b/src/main/scala/firrtl2/stage/Forms.scala index c589323bc..090daae2f 100644 --- a/src/main/scala/firrtl2/stage/Forms.scala +++ b/src/main/scala/firrtl2/stage/Forms.scala @@ -110,7 +110,6 @@ object Forms { Dependency[firrtl2.transforms.InlineAcrossCastsTransform], Dependency[firrtl2.transforms.LegalizeClocksAndAsyncResetsTransform], Dependency[firrtl2.transforms.FlattenRegUpdate], - Dependency(passes.VerilogModulusCleanup), Dependency[firrtl2.transforms.VerilogRename], Dependency(passes.VerilogPrep), Dependency[firrtl2.AddDescriptionNodes] diff --git a/src/main/scala/firrtl2/stage/phases/Compiler.scala b/src/main/scala/firrtl2/stage/phases/Compiler.scala index 28f378d66..22af1a122 100644 --- a/src/main/scala/firrtl2/stage/phases/Compiler.scala +++ b/src/main/scala/firrtl2/stage/phases/Compiler.scala @@ -147,7 +147,6 @@ class Compiler extends Phase with Translator[AnnotationSeq, Seq[CompilerRun]] { } private def compilerToTransforms(a: FirrtlCompiler): Seq[TransformDependency] = a match { - case _: firrtl2.NoneCompiler => Forms.ChirrtlForm case _: firrtl2.HighFirrtlCompiler => Forms.MinimalHighForm case _: firrtl2.MiddleFirrtlCompiler => Forms.MidForm case _: firrtl2.LowFirrtlCompiler => Forms.LowForm diff --git a/src/main/scala/firrtl2/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl2/transforms/DeadCodeElimination.scala index d6e31b31b..3b20c5117 100644 --- a/src/main/scala/firrtl2/transforms/DeadCodeElimination.scala +++ b/src/main/scala/firrtl2/transforms/DeadCodeElimination.scala @@ -43,7 +43,6 @@ class DeadCodeElimination extends Transform with RegisteredTransform with Depend Dependency[firrtl2.transforms.BlackBoxSourceHelper], Dependency[firrtl2.transforms.ReplaceTruncatingArithmetic], Dependency[firrtl2.transforms.FlattenRegUpdate], - Dependency(passes.VerilogModulusCleanup), Dependency[firrtl2.transforms.VerilogRename], Dependency(passes.VerilogPrep), Dependency[firrtl2.AddDescriptionNodes] diff --git a/src/main/scala/firrtl2/transforms/IdentityTransform.scala b/src/main/scala/firrtl2/transforms/IdentityTransform.scala deleted file mode 100644 index e161f7c20..000000000 --- a/src/main/scala/firrtl2/transforms/IdentityTransform.scala +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package firrtl2.transforms - -import firrtl2.{CircuitForm, CircuitState, Transform} - -/** Transform that applies an identity function. This returns an unmodified [[CircuitState]]. - * @param form the input and output [[CircuitForm]] - */ -@deprecated( - "mix-in firrtl.options.IdentityLike[CircuitState]. IdentityTransform will be removed in 1.4.", - "FIRRTL 1.3" -) -class IdentityTransform(form: CircuitForm) extends Transform { - - final override def inputForm: CircuitForm = form - - final override def outputForm: CircuitForm = form - - final def execute(state: CircuitState): CircuitState = state - -} diff --git a/src/main/scala/firrtl2/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl2/transforms/RemoveKeywordCollisions.scala index c10599a16..054235138 100644 --- a/src/main/scala/firrtl2/transforms/RemoveKeywordCollisions.scala +++ b/src/main/scala/firrtl2/transforms/RemoveKeywordCollisions.scala @@ -39,8 +39,7 @@ class VerilogRename extends RemoveKeywordCollisions(v_keywords) { Dependency[InlineBitExtractionsTransform], Dependency[InlineAcrossCastsTransform], Dependency[LegalizeClocksAndAsyncResetsTransform], - Dependency[FlattenRegUpdate], - Dependency(passes.VerilogModulusCleanup) + Dependency[FlattenRegUpdate] ) override def optionalPrerequisites = firrtl2.stage.Forms.LowFormOptimized diff --git a/src/test/scala/firrtl2/stage/phases/tests/DriverCompatibilitySpec.scala b/src/test/scala/firrtl2/stage/phases/tests/DriverCompatibilitySpec.scala index 235648b56..a78388152 100644 --- a/src/test/scala/firrtl2/stage/phases/tests/DriverCompatibilitySpec.scala +++ b/src/test/scala/firrtl2/stage/phases/tests/DriverCompatibilitySpec.scala @@ -139,8 +139,7 @@ class DriverCompatibilitySpec extends AnyFlatSpec with Matchers with PrivateMeth behavior.of(classOf[AddImplicitEmitter].toString) - val (nc, hfc, mfc, lfc, vc, svc) = ( - new NoneCompiler, + val (hfc, mfc, lfc, vc, svc) = ( new HighFirrtlCompiler, new MiddleFirrtlCompiler, new LowFirrtlCompiler, @@ -151,7 +150,6 @@ class DriverCompatibilitySpec extends AnyFlatSpec with Matchers with PrivateMeth it should "convert CompilerAnnotations into EmitCircuitAnnotations without EmitOneFilePerModuleAnnotation" in new PhaseFixture(new AddImplicitEmitter) { val annotations = Seq( - CompilerAnnotation(nc), CompilerAnnotation(hfc), CompilerAnnotation(mfc), CompilerAnnotation(lfc), @@ -170,7 +168,6 @@ class DriverCompatibilitySpec extends AnyFlatSpec with Matchers with PrivateMeth new PhaseFixture(new AddImplicitEmitter) { val annotations = Seq( EmitOneFilePerModuleAnnotation, - CompilerAnnotation(nc), CompilerAnnotation(hfc), CompilerAnnotation(mfc), CompilerAnnotation(lfc), diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala index 8e9c746f7..ba24cc72d 100644 --- a/src/test/scala/firrtlTests/AttachSpec.scala +++ b/src/test/scala/firrtlTests/AttachSpec.scala @@ -270,7 +270,7 @@ class AttachAnalogSpec extends FirrtlFlatSpec { } "Connecting analog types" should "throw an exception" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes) val input = """circuit Unit : | module Unit : @@ -285,7 +285,7 @@ class AttachAnalogSpec extends FirrtlFlatSpec { } "Declaring register with analog types" should "throw an exception" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes) val input = """circuit Unit : | module Unit : @@ -299,7 +299,7 @@ class AttachAnalogSpec extends FirrtlFlatSpec { } "Declaring memory with analog types" should "throw an exception" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes) val input = """circuit Unit : | module Unit : @@ -318,7 +318,7 @@ class AttachAnalogSpec extends FirrtlFlatSpec { } "Declaring node with analog types" should "throw an exception" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes) val input = """circuit Unit : | module Unit : @@ -332,7 +332,7 @@ class AttachAnalogSpec extends FirrtlFlatSpec { } "Attaching a non-analog expression" should "not be ok" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes) val input = """circuit Unit : | module Unit : @@ -352,7 +352,7 @@ class AttachAnalogSpec extends FirrtlFlatSpec { } "Inequal attach widths" should "throw an exception" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, new InferWidths, CheckWidths) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes, new InferWidths, CheckWidths) val input = """circuit Unit : | module Unit : diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala index 8fb22a5e6..cd0b3e910 100644 --- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala +++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala @@ -8,7 +8,6 @@ import firrtl2.testutils._ class CheckInitializationSpec extends FirrtlFlatSpec { private val passes = Seq( - ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala index 535e6ea2d..fa15c63a1 100644 --- a/src/test/scala/firrtlTests/CheckSpec.scala +++ b/src/test/scala/firrtlTests/CheckSpec.scala @@ -15,14 +15,13 @@ import firrtl2.passes.{ Pass, PassException, ResolveFlows, - ResolveKinds, - ToWorkingIR + ResolveKinds } import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers class CheckSpec extends AnyFlatSpec with Matchers { - val defaultPasses = Seq(ToWorkingIR, CheckHighForm) + val defaultPasses = Seq(CheckHighForm) def checkHighInput(input: String) = { defaultPasses.foldLeft(Parser.parse(input.split("\n").toIterator)) { (c: Circuit, p: Pass) => p.run(c) @@ -56,7 +55,7 @@ class CheckSpec extends AnyFlatSpec with Matchers { } "Memories with zero write latency" should "throw an exception" in { - val passes = Seq(ToWorkingIR, CheckHighForm) + val passes = Seq(CheckHighForm) val input = """circuit Unit : | module Unit : @@ -283,7 +282,6 @@ class CheckSpec extends AnyFlatSpec with Matchers { "Clock Types" should "be connectable" in { val passes = Seq( - ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, @@ -324,7 +322,7 @@ class CheckSpec extends AnyFlatSpec with Matchers { } "Clocks with types other than ClockType" should "throw an exception" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes) val input = """ |circuit Top : @@ -347,7 +345,7 @@ class CheckSpec extends AnyFlatSpec with Matchers { } "Illegal reset type" should "throw an exception" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes) val input = """ |circuit Top : @@ -406,7 +404,7 @@ class CheckSpec extends AnyFlatSpec with Matchers { for ((description, input) <- CheckSpec.nonUniqueExamples) { it should s"be asserted for $description" in { assertThrows[CheckHighForm.NotUniqueException] { - Seq(ToWorkingIR, CheckHighForm).foldLeft(Parser.parse(input)) { case (c, tx) => tx.run(c) } + Seq(CheckHighForm).foldLeft(Parser.parse(input)) { case (c, tx) => tx.run(c) } } } } diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala index a8c55f886..bdcb8a410 100644 --- a/src/test/scala/firrtlTests/ChirrtlSpec.scala +++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala @@ -12,7 +12,6 @@ class ChirrtlSpec extends FirrtlFlatSpec { CInferTypes, CInferMDir, RemoveCHIRRTL, - ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, @@ -72,7 +71,7 @@ class ChirrtlSpec extends FirrtlFlatSpec { for ((description, input) <- CheckSpec.nonUniqueExamples) { it should s"be asserted for $description" in { assertThrows[CheckHighForm.NotUniqueException] { - Seq(ToWorkingIR, CheckHighForm).foldLeft(Parser.parse(input)) { case (c, tx) => tx.run(c) } + Seq(CheckHighForm).foldLeft(Parser.parse(input)) { case (c, tx) => tx.run(c) } } } } diff --git a/src/test/scala/firrtlTests/ClockListTests.scala b/src/test/scala/firrtlTests/ClockListTests.scala index 281e3c660..cf8c1d40d 100644 --- a/src/test/scala/firrtlTests/ClockListTests.scala +++ b/src/test/scala/firrtlTests/ClockListTests.scala @@ -22,7 +22,6 @@ class ClockListTests extends FirrtlFlatSpec { } def passes = Seq( - ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 696347e52..ae25695f3 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -11,7 +11,7 @@ import firrtl2.stage.DisableFold class ConstantPropagationSpec extends FirrtlFlatSpec { val transforms: Seq[Transform] = - Seq(ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, new InferWidths, new ConstantPropagation) + Seq(ResolveKinds, InferTypes, ResolveFlows, new InferWidths, new ConstantPropagation) protected def exec(input: String, annos: Seq[Annotation] = Nil) = { transforms .foldLeft(CircuitState(parse(input), UnknownForm, AnnotationSeq(annos))) { (c: CircuitState, t: Transform) => diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala index d023ab478..09a66d680 100644 --- a/src/test/scala/firrtlTests/CustomTransformSpec.scala +++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala @@ -8,7 +8,7 @@ import firrtl2.passes.Pass import firrtl2.ir._ import firrtl2.stage.{FirrtlSourceAnnotation, FirrtlStage, RunFirrtlTransformAnnotation} import firrtl2.options.Dependency -import firrtl2.transforms.{IdentityTransform, LegalizeAndReductionsTransform} +import firrtl2.transforms.{LegalizeAndReductionsTransform} import firrtl2.testutils._ import firrtl2.transforms.formal.ConvertAsserts @@ -99,10 +99,6 @@ object CustomTransformSpec { } } - class IdentityLowForm extends IdentityTransform(LowForm) { - override val name = ">>>>> IdentityLowForm <<<<<" - } - object Foo { class A extends Transform { def inputForm = HighForm @@ -151,25 +147,6 @@ class CustomTransformSpec extends FirrtlFlatSpec { ) } - they should "run right before the emitter* when inputForm=LowForm" in { - - Seq( - Dependency[LowFirrtlEmitter], - Dependency[MinimumVerilogEmitter], - Dependency[VerilogEmitter], - Dependency[SystemVerilogEmitter] - ).foreach { emitter => - val custom = Dependency[IdentityLowForm] - val tm = new firrtl2.stage.transforms.Compiler(custom :: emitter :: Nil) - info(s"when using ${emitter.getObject().name}") - tm.flattenedTransformOrder - .map(Dependency.fromTransform) - .sliding(2) - .toList should contain(Seq(custom, emitter)) - } - - } - they should "work if placed inside an object" in { val input = """|circuit Foo: diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala index d8c8cb621..e4e0eacb8 100644 --- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala +++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala @@ -8,7 +8,6 @@ import firrtl2.testutils._ class ExpandWhensSpec extends FirrtlFlatSpec { private val transforms = Seq( - ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala index e57bd43c5..ffb23759a 100644 --- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala +++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala @@ -191,7 +191,7 @@ circuit Top : f <= c """.stripMargin - val circuit = InferTypes.run(ToWorkingIR.run(parse(input))) + val circuit = InferTypes.run(parse(input)) val m = circuit.modules.head.asInstanceOf[ir.Module] val connects = AnalysisUtils.getConnects(m) val calculatedOrigin = AnalysisUtils.getOrigin(connects, "f").serialize diff --git a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala index a40056512..ba27f8739 100644 --- a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala +++ b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala @@ -7,7 +7,7 @@ import firrtl2.passes._ import firrtl2.testutils._ class ReplaceAccessesSpec extends FirrtlFlatSpec { - val transforms = Seq(ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, new InferWidths, ReplaceAccesses) + val transforms = Seq(ResolveKinds, InferTypes, ResolveFlows, new InferWidths, ReplaceAccesses) protected def exec(input: String) = { transforms .foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, t: Transform) => diff --git a/src/test/scala/firrtlTests/UniquifySpec.scala b/src/test/scala/firrtlTests/UniquifySpec.scala deleted file mode 100644 index cc2178990..000000000 --- a/src/test/scala/firrtlTests/UniquifySpec.scala +++ /dev/null @@ -1,321 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package firrtlTests - -import firrtl2.Parser -import firrtl2.passes._ -import firrtl2._ -import firrtl2.annotations._ -import firrtl2.annotations.TargetToken._ -import firrtl2.transforms.DontTouchAnnotation -import firrtl2.util.TestOptions -import firrtl2.testutils._ - -class UniquifySpec extends FirrtlFlatSpec { - - private def transforms = Seq( - ToWorkingIR, - CheckHighForm, - ResolveKinds, - InferTypes, - Uniquify - ) - - private def executeTest(input: String, expected: Seq[String]): Unit = - executeTest(input, expected, Seq.empty, Seq.empty) - private def executeTest( - input: String, - expected: Seq[String], - inputAnnos: Seq[Annotation], - expectedAnnos: Seq[Annotation] - ): Unit = { - val circuit = Parser.parse(input.split("\n").toIterator) - val result = transforms.foldLeft(CircuitState(circuit, UnknownForm, inputAnnos)) { - (c: CircuitState, p: Transform) => p.runTransform(c) - } - val c = result.circuit - val lines = c.serialize.split("\n").map(normalized) - - expected.foreach { e => - lines should contain(e) - } - - result.annotations.toSeq should equal(expectedAnnos) - } - - behavior.of("Uniquify") - - it should "rename colliding ports" in { - val input = - """circuit Test : - | module Test : - | input a : { flip b : UInt<1>, c : { d : UInt<2>, flip e : UInt<3>}[2], c_1_e : UInt<4>}[2] - | output a_0_c_ : UInt<5> - | output a__0 : UInt<6> - """.stripMargin - val expected = Seq( - "input a__ : { flip b : UInt<1>, c_ : { d : UInt<2>, flip e : UInt<3>}[2], c_1_e : UInt<4>}[2]", - "output a_0_c_ : UInt<5>", - "output a__0 : UInt<6>" - ).map(normalized) - - val inputAnnos = Seq( - DontTouchAnnotation(ReferenceTarget("Test", "Test", Seq.empty, "a", Seq(Index(0), Field("b")))), - DontTouchAnnotation( - ReferenceTarget("Test", "Test", Seq.empty, "a", Seq(Index(0), Field("c"), Index(0), Field("e"))) - ) - ) - - val expectedAnnos = Seq( - DontTouchAnnotation(ReferenceTarget("Test", "Test", Seq.empty, "a__", Seq(Index(0), Field("b")))), - DontTouchAnnotation( - ReferenceTarget("Test", "Test", Seq.empty, "a__", Seq(Index(0), Field("c_"), Index(0), Field("e"))) - ) - ) - - executeTest(input, expected, inputAnnos, expectedAnnos) - } - - it should "rename colliding registers" in { - val input = - """circuit Test : - | module Test : - | input clock : Clock - | reg a : { b : UInt<1>, c : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2], clock - | reg a_0_c_ : UInt<5>, clock - | reg a__0 : UInt<6>, clock - """.stripMargin - val expected = Seq( - "reg a__ : { b : UInt<1>, c_ : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2], clock with :", - "reg a_0_c_ : UInt<5>, clock with :", - "reg a__0 : UInt<6>, clock with :" - ).map(normalized) - - executeTest(input, expected) - } - - it should "rename colliding nodes" in { - val input = - """circuit Test : - | module Test : - | input clock : Clock - | reg x : { b : UInt<1>, c : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2], clock - | node a = x - | node a_0_c_ = a[0].b - | node a__0 = a[1].c[0].d - """.stripMargin - val expected = Seq("node a__ = x").map(normalized) - - executeTest(input, expected) - } - - it should "rename DefRegister expressions: clock, reset, and init" in { - val input = - """circuit Test : - | module Test : - | input clock : Clock[2] - | input clock_0 : Clock - | input reset : { a : UInt<1>, b : UInt<1>} - | input reset_a : UInt<1> - | input init : { a : UInt<4>, b : { c : UInt<4>, d : UInt<4>}[2], b_1_c : UInt<4>}[4] - | input init_0_a : UInt<4> - | reg foo : UInt<4>, clock[1], with : - | reset => (reset.a, init[3].b[1].d) - """.stripMargin - val expected = Seq( - "reg foo : UInt<4>, clock_[1] with :", - "reset => (reset_.a, init_[3].b_[1].d)" - ).map(normalized) - - executeTest(input, expected) - } - - it should "rename ports before statements" in { - val input = - """circuit Test : - | module Test : - | input data : { a : UInt<4>, b : UInt<4>}[2] - | node data_0_a = data[0].a - """.stripMargin - val expected = Seq( - "input data : { a : UInt<4>, b : UInt<4>}[2]", - "node data_0_a_ = data[0].a" - ).map(normalized) - - executeTest(input, expected) - } - - it should "rename node expressions" in { - val input = - """circuit Test : - | module Test : - | input data : { a : UInt<4>, b : UInt<4>[2]} - | input data_a : UInt<4> - | input data__b_1 : UInt<4> - | node foo = data.a - | node bar = data.b[1] - """.stripMargin - val expected = Seq("node foo = data__.a", "node bar = data__.b[1]").map(normalized) - - executeTest(input, expected) - } - - it should "rename both side of connects" in { - val input = - """circuit Test : - | module Test : - | input a : { b : UInt<1>, flip c : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2] - | output a_0_b : UInt<1> - | input a__0_c_ : { d : UInt<2>, e : UInt<3>}[2] - | a_0_b <= a[0].b - | a[0].c <= a__0_c_ - """.stripMargin - val expected = Seq("a_0_b <= a__[0].b", "a__[0].c_ <= a__0_c_").map(normalized) - - executeTest(input, expected) - } - - it should "rename SubAccesses" in { - val input = - """circuit Test : - | module Test : - | input a : { b : UInt<1>, c : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2] - | output a_0_b : UInt<2> - | input i : UInt<1>[2] - | output i_0 : UInt<1> - | a_0_b <= a.c[i[1]].d - """.stripMargin - val expected = Seq("a_0_b <= a_.c_[i_[1]].d").map(normalized) - - executeTest(input, expected) - } - - it should "rename deeply nested expressions" in { - val input = - """circuit Test : - | module Test : - | input a : { b : UInt<1>, flip c : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2] - | output a_0_b : UInt<1> - | input a__0_c_ : { d : UInt<2>, e : UInt<3>}[2] - | a_0_b <= mux(a[UInt(0)].c_1_e, or(a[or(a[0].b, a[1].b)].b, xorr(a[0].c_1_e)), orr(cat(a__0_c_[0].e, a[1].c_1_e))) - """.stripMargin - val expected = Seq( - "a_0_b <= mux(a__[UInt<1>(\"h0\")].c_1_e, or(a__[or(a__[0].b, a__[1].b)].b, xorr(a__[0].c_1_e)), orr(cat(a__0_c_[0].e, a__[1].c_1_e)))" - ).map(normalized) - - executeTest(input, expected) - } - - it should "rename memories" in { - val input = - """circuit Test : - | module Test : - | input clock : Clock - | mem mem : - | data-type => { a : UInt<8>, b : UInt<8>[2]}[2] - | depth => 32 - | read-latency => 0 - | write-latency => 1 - | reader => read - | writer => write - | node mem_0_b = mem.read.data[0].b - | - | mem.read.addr is invalid - | mem.read.en <= UInt(1) - | mem.read.clk <= clock - | mem.write.data is invalid - | mem.write.mask is invalid - | mem.write.addr is invalid - | mem.write.en <= UInt(0) - | mem.write.clk <= clock - """.stripMargin - val expected = Seq("mem mem_ :", "node mem_0_b = mem_.read.data[0].b", "mem_.read.addr is invalid").map(normalized) - - executeTest(input, expected) - } - - it should "rename aggregate typed memories" in { - val input = - """circuit Test : - | module Test : - | input clock : Clock - | mem mem : - | data-type => { a : UInt<8>, b : UInt<8>[2], b_0 : UInt<8> } - | depth => 32 - | read-latency => 0 - | write-latency => 1 - | reader => read - | writer => write - | node x = mem.read.data.b[0] - | - | mem.read.addr is invalid - | mem.read.en <= UInt(1) - | mem.read.clk <= clock - | mem.write.data is invalid - | mem.write.mask is invalid - | mem.write.addr is invalid - | mem.write.en <= UInt(0) - | mem.write.clk <= clock - """.stripMargin - val expected = - Seq("data-type => { a : UInt<8>, b_ : UInt<8>[2], b_0 : UInt<8>}", "node x = mem.read.data.b_[0]").map(normalized) - - executeTest(input, expected) - } - - it should "rename instances and their ports" in { - val input = - """circuit Test : - | module Other : - | input a : { b : UInt<4>, c : UInt<4> } - | output a_b : UInt<4> - | a_b <= a.b - | - | module Test : - | node x = UInt(6) - | inst mod of Other - | mod.a.b <= x - | mod.a.c <= x - | node mod_a_b = mod.a_b - """.stripMargin - val expected = - Seq("inst mod_ of Other", "mod_.a_.b <= x", "mod_.a_.c <= x", "node mod_a_b = mod_.a_b").map(normalized) - - executeTest(input, expected) - } - - it should "quickly rename deep bundles" in { - val depth = 500 - // We previously used a fixed time to determine if this test passed or failed. - // This test would pass under normal conditions, but would fail during coverage tests. - // Instead of using a fixed time, we run the test once (with a rename depth of 1), and record the time, - // then run it again with a depth of 500 and verify that the difference is below a fixed threshold. - // Additionally, since executions times vary significantly under coverage testing, we check a global - // to see if timing measurements are accurate enough to enforce the timing checks. - val threshold = depth * 2.0 - // As of 20-Feb-2019, this still fails occasionally: - // [info] 9038.99351 was not less than 6113.865 (UniquifySpec.scala:317) - // Run the "quick" test three times and choose the longest time as the basis. - val nCalibrationRuns = 3 - def mkType(i: Int): String = { - if (i == 0) "UInt<8>" else s"{x: ${mkType(i - 1)}}" - } - val timesMs = ( - for (depth <- (List.fill(nCalibrationRuns)(1) :+ depth)) yield { - val input = s"""circuit Test: - | module Test : - | input in: ${mkType(depth)} - | output out: ${mkType(depth)} - | out <= in - |""".stripMargin - val (ms, _) = Utils.time(compileToVerilog(input)) - ms - } - ).toArray - // The baseMs will be the maximum of the first calibration runs - val baseMs = timesMs.slice(0, nCalibrationRuns - 1).max - val renameMs = timesMs(nCalibrationRuns) - if (TestOptions.accurateTiming) - renameMs shouldBe <(baseMs * threshold) - } -} diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index d6045c964..dcf3b1a26 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -33,7 +33,7 @@ class UnitTests extends FirrtlFlatSpec { } "Pull muxes" should "not be exponential in runtime" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, PullMuxes) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes, PullMuxes) val input = """circuit Unit : | module Unit : @@ -46,7 +46,7 @@ class UnitTests extends FirrtlFlatSpec { } "Connecting bundles of different types" should "throw an exception" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes) val input = """circuit Unit : | module Unit : @@ -61,7 +61,7 @@ class UnitTests extends FirrtlFlatSpec { } "Initializing a register with a different type" should "throw an exception" in { - val passes = Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes) + val passes = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes) val input = """circuit Unit : | module Unit : @@ -89,7 +89,7 @@ class UnitTests extends FirrtlFlatSpec { |""".stripMargin "Emitting a nested expression" should "compile" in { - val passes = Seq(ToWorkingIR, InferTypes, ResolveKinds) + val passes = Seq(InferTypes, ResolveKinds) val c = Parser.parse(splitExpTestCode.split("\n").toIterator) val c2 = passes.foldLeft(c)((c, p) => p.run(c)) val writer = new StringWriter() @@ -98,7 +98,6 @@ class UnitTests extends FirrtlFlatSpec { "Simple compound expressions" should "be split" in { val passes = Seq( - ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, @@ -122,7 +121,6 @@ class UnitTests extends FirrtlFlatSpec { "Smaller widths" should "be explicitly padded" in { val passes = Seq( - ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, @@ -143,7 +141,6 @@ class UnitTests extends FirrtlFlatSpec { "Indexes into sub-accesses" should "be dealt with" in { val passes = Seq( - ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, @@ -182,7 +179,7 @@ class UnitTests extends FirrtlFlatSpec { } "Oversized bit select" should "throw an exception" in { - val passes = Seq(ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, new InferWidths, CheckWidths) + val passes = Seq(ResolveKinds, InferTypes, ResolveFlows, new InferWidths, CheckWidths) val input = """circuit Unit : | module Unit : @@ -195,7 +192,7 @@ class UnitTests extends FirrtlFlatSpec { } "Oversized head select" should "throw an exception" in { - val passes = Seq(ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, new InferWidths, CheckWidths) + val passes = Seq(ResolveKinds, InferTypes, ResolveFlows, new InferWidths, CheckWidths) val input = """circuit Unit : | module Unit : @@ -209,7 +206,7 @@ class UnitTests extends FirrtlFlatSpec { "zero head select" should "return an empty module" in { val passes = - Seq(ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, new InferWidths, CheckWidths, new DeadCodeElimination) + Seq(ResolveKinds, InferTypes, ResolveFlows, new InferWidths, CheckWidths, new DeadCodeElimination) val input = """circuit Unit : | module Unit : @@ -222,7 +219,7 @@ class UnitTests extends FirrtlFlatSpec { } "Oversized tail select" should "throw an exception" in { - val passes = Seq(ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, new InferWidths, CheckWidths) + val passes = Seq(ResolveKinds, InferTypes, ResolveFlows, new InferWidths, CheckWidths) val input = """circuit Unit : | module Unit : @@ -236,7 +233,7 @@ class UnitTests extends FirrtlFlatSpec { "max tail select" should "return an empty module" in { val passes = - Seq(ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, new InferWidths, CheckWidths, new DeadCodeElimination) + Seq(ResolveKinds, InferTypes, ResolveFlows, new InferWidths, CheckWidths, new DeadCodeElimination) val input = """circuit Unit : | module Unit : @@ -318,7 +315,6 @@ class UnitTests extends FirrtlFlatSpec { "Out of bound accesses" should "be invalid" in { val passes = Seq( - ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index 66bfc3853..660eddbce 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -309,7 +309,6 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { // We do just a few passes instead of using the VerilogCompiler to ensure that the pad actually // reaches the VerilogEmitter and isn't removed by an optimization transform val passes = Seq( - ToWorkingIR, ResolveKinds, InferTypes ) @@ -507,7 +506,7 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { | tmp <= mux(eq(sel, UInt<2>(0)), in_0, _GEN_1) | out <= tmp |""".stripMargin - val circuit = Seq(ToWorkingIR, ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } + val circuit = Seq(ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } val state = CircuitState(circuit, LowForm, Seq(EmitCircuitAnnotation(classOf[VerilogEmitter]))) val result = (new VerilogEmitter).execute(state) result should containLine("if (sel == 2'h0) begin") @@ -528,7 +527,7 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { | tmp <= mux(eq(sel, UInt<1>(0)), in, tmp) | out <= tmp |""".stripMargin - val circuit = Seq(ToWorkingIR, ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } + val circuit = Seq(ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } val state = CircuitState(circuit, LowForm, Seq(EmitCircuitAnnotation(classOf[VerilogEmitter]))) val result = (new VerilogEmitter).execute(state) result should not(containLine("tmp <= tmp")) @@ -546,7 +545,7 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { | tmp <= mux(eq(sel, UInt<1>(0)), tmp, in) | out <= tmp |""".stripMargin - val circuit = Seq(ToWorkingIR, ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } + val circuit = Seq(ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } val state = CircuitState(circuit, LowForm, Seq(EmitCircuitAnnotation(classOf[VerilogEmitter]))) val result = (new VerilogEmitter).execute(state) result should containLine("if (!(sel == 1'h0)) begin") @@ -565,7 +564,7 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { | tmp <= mux(eq(sel, UInt<1>(0)), tmp, tmp) | out <= tmp |""".stripMargin - val circuit = Seq(ToWorkingIR, ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } + val circuit = Seq(ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } val state = CircuitState(circuit, LowForm, Seq(EmitCircuitAnnotation(classOf[VerilogEmitter]))) val result = (new VerilogEmitter).execute(state) result should not(containLine("tmp <= tmp")) @@ -604,7 +603,7 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { | tmp <= mux(reset, m0, m1) | out <= tmp |""".stripMargin - val circuit = Seq(ToWorkingIR, ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } + val circuit = Seq(ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } val state = CircuitState(circuit, LowForm, Seq(EmitCircuitAnnotation(classOf[VerilogEmitter]))) val result = (new VerilogEmitter).execute(state) /* The Verilog string is used to check for no whitespace between "else" and "if". */ @@ -874,7 +873,7 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { | mem.r.clk <= clock | out <= mem.r.data |""".stripMargin - val circuit = Seq(ToWorkingIR, ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } + val circuit = Seq(ResolveKinds, InferTypes).foldLeft(parse(input)) { case (c, p) => p.run(c) } val state = CircuitState( circuit, LowForm, diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala index 10deb5f2c..0017e8064 100644 --- a/src/test/scala/firrtlTests/WidthSpec.scala +++ b/src/test/scala/firrtlTests/WidthSpec.scala @@ -20,8 +20,7 @@ class WidthSpec extends FirrtlFlatSpec { } } - private val inferPasses = - Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths) + private val inferPasses = Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths) private val inferAndCheckPasses = inferPasses :+ CheckWidths diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala index f19411099..e5e438177 100644 --- a/src/test/scala/firrtlTests/WiringTests.scala +++ b/src/test/scala/firrtlTests/WiringTests.scala @@ -24,7 +24,6 @@ class WiringTests extends FirrtlFlatSpec { } def passes = Seq( - ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, diff --git a/src/test/scala/firrtlTests/ZeroLengthVecsSpec.scala b/src/test/scala/firrtlTests/ZeroLengthVecsSpec.scala index 166a7bc8e..f56df8cef 100644 --- a/src/test/scala/firrtlTests/ZeroLengthVecsSpec.scala +++ b/src/test/scala/firrtlTests/ZeroLengthVecsSpec.scala @@ -7,7 +7,7 @@ import firrtl2.passes._ import firrtl2.testutils.FirrtlFlatSpec class ZeroLengthVecsSpec extends FirrtlFlatSpec { - val transforms = Seq(ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, new InferWidths, ZeroLengthVecs, CheckTypes) + val transforms = Seq(ResolveKinds, InferTypes, ResolveFlows, new InferWidths, ZeroLengthVecs, CheckTypes) protected def exec(input: String) = { transforms .foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, t: Transform) => diff --git a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala index 49fdc69bd..169e39ef0 100644 --- a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala +++ b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala @@ -33,7 +33,7 @@ circuit Top : module Child2 : skip """ - val circuit = ToWorkingIR.run(parse(input)) + val circuit = parse(input) val graph = new InstanceGraph(circuit).graph.transformNodes(_.module) getEdgeSet(graph) shouldBe Map( "Top" -> Set("Child1", "Child2"), @@ -68,7 +68,7 @@ circuit Top : skip """ - val circuit = ToWorkingIR.run(parse(input)) + val circuit = parse(input) val iGraph = new InstanceGraph(circuit) iGraph.findInstancesInHierarchy("Top") shouldBe Seq(Seq(WDefInstance("Top", "Top"))) iGraph.findInstancesInHierarchy("Child1") shouldBe Seq(Seq(WDefInstance("Top", "Top"), WDefInstance("c", "Child1"))) @@ -103,7 +103,7 @@ circuit Top : skip """ - val circuit = ToWorkingIR.run(parse(input)) + val circuit = parse(input) val graph = new InstanceGraph(circuit).graph.transformNodes(_.module) getEdgeSet(graph) shouldBe Map( "Top" -> Set("Child1"), @@ -131,7 +131,7 @@ circuit Top : inst f of Foo inst b of Bar """ - val circuit = ToWorkingIR.run(parse(input)) + val circuit = parse(input) val graph = (new InstanceGraph(circuit)).graph // Create graphs with edges from child to parent module @@ -165,7 +165,7 @@ circuit Top : | module Child2 : | skip |""".stripMargin - val circuit = ToWorkingIR.run(parse(input)) + val circuit = parse(input) val instGraph = new InstanceGraph(circuit) val childMap = instGraph.getChildrenInstances childMap.keys.toSeq should equal(Seq("Top", "Child1", "Child1a", "Child1b", "Child2")) @@ -186,7 +186,7 @@ circuit Top : | module Child : | skip |""".stripMargin - val circuit = ToWorkingIR.run(parse(input)) + val circuit = parse(input) val instGraph = new InstanceGraph(circuit) val childMap = instGraph.getChildrenInstances val insts = childMap("Top").toSeq.map(_.name) @@ -207,7 +207,7 @@ circuit Top : | module Child : | skip |""".stripMargin - val circuit = ToWorkingIR.run(parse(input)) + val circuit = parse(input) val instGraph = new InstanceGraph(circuit) val hier = instGraph.fullHierarchy hier.keys.toSeq.map(_.name) should equal(Seq("Top", "a", "b", "c", "d", "e")) @@ -221,7 +221,7 @@ circuit Top : | module Foo: | skip |""".stripMargin - val iGraph = new InstanceGraph(ToWorkingIR.run(parse(input))) + val iGraph = new InstanceGraph(parse(input)) val expectedCounts = Map(OfModule("Foo") -> 1) iGraph.staticInstanceCount should be(expectedCounts) } @@ -240,7 +240,7 @@ circuit Top : | inst bar1 of Bar | inst bar2 of Bar |""".stripMargin - val iGraph = new InstanceGraph(ToWorkingIR.run(parse(input))) + val iGraph = new InstanceGraph(parse(input)) val expectedCounts = Map(OfModule("Foo") -> 1, OfModule("Bar") -> 2, OfModule("Baz") -> 3) iGraph.staticInstanceCount should be(expectedCounts) } @@ -253,7 +253,7 @@ circuit Top : | module Foo: | skip |""".stripMargin - val iGraph = new InstanceGraph(ToWorkingIR.run(parse(input))) + val iGraph = new InstanceGraph(parse(input)) val expectedCounts = Map(OfModule("Foo") -> 1, OfModule("Bar") -> 0) iGraph.staticInstanceCount should be(expectedCounts) } @@ -270,7 +270,7 @@ circuit Top : | module Top: | inst reachable of Reachable |""".stripMargin - val iGraph = new InstanceGraph(ToWorkingIR.run(parse(input))) + val iGraph = new InstanceGraph(parse(input)) iGraph.modules should contain theSameElementsAs Seq(OfModule("Top"), OfModule("Reachable"), OfModule("Unreachable")) iGraph.reachableModules should contain theSameElementsAs Seq(OfModule("Top"), OfModule("Reachable")) iGraph.unreachableModules should contain theSameElementsAs Seq(OfModule("Unreachable")) diff --git a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala index 9e13d00de..a17b555cd 100644 --- a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala +++ b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala @@ -365,7 +365,7 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers { | inst bar of Bar |""".stripMargin - CircuitState(passes.ToWorkingIR.run(Parser.parse(input)), UnknownForm, Nil) + CircuitState(Parser.parse(input), UnknownForm, Nil) .resolvePaths(Seq(CircuitTarget("Foo").module("Foo").instOf("bar", "Bar"))) .annotations .collect { case a: firrtl2.annotations.transforms.ResolvePaths => a } should be(empty) @@ -389,7 +389,7 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers { | inst bar of Bar___Foo_bar | inst baz of Bar""".stripMargin val Bar_x = CircuitTarget("Foo").module("Bar").ref("x") - val output = CircuitState(passes.ToWorkingIR.run(Parser.parse(input)), UnknownForm, Seq(DontTouchAnnotation(Bar_x))) + val output = CircuitState(Parser.parse(input), UnknownForm, Seq(DontTouchAnnotation(Bar_x))) .resolvePaths(Seq(CircuitTarget("Foo").module("Foo").instOf("bar", "Bar"))) val parsedCheck = Parser.parse(check) @@ -423,7 +423,7 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers { ) val dontTouches = targets.map(t => DontTouchAnnotation(t.ref("foo"))) val inputCircuit = Parser.parse(input) - val output = CircuitState(passes.ToWorkingIR.run(inputCircuit), UnknownForm, dontTouches) + val output = CircuitState(inputCircuit, UnknownForm, dontTouches) .resolvePaths(targets) info(output.circuit.serialize) @@ -462,7 +462,7 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers { CircuitTarget("FooBar").module("FooBar").instOf("foo", "Foo").instOf("barBar", "Bar") ) val dontTouches = targets.map(t => DontTouchAnnotation(t.ref("baz"))) - val output = CircuitState(passes.ToWorkingIR.run(Parser.parse(input)), UnknownForm, dontTouches) + val output = CircuitState(Parser.parse(input), UnknownForm, dontTouches) .resolvePaths(targets) info(output.circuit.serialize) @@ -508,7 +508,7 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers { DontTouchAnnotation(bazzz.ref("foo")) ) val inputCircuit = Parser.parse(input) - val output = CircuitState(passes.ToWorkingIR.run(inputCircuit), UnknownForm, annos) + val output = CircuitState(inputCircuit, UnknownForm, annos) .resolvePaths(Seq(baz, bazzz)) info(output.circuit.serialize) @@ -546,7 +546,7 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers { DontTouchAnnotation(baz.ref("foo")) ) val inputCircuit = Parser.parse(input) - val output = CircuitState(passes.ToWorkingIR.run(inputCircuit), UnknownForm, annos) + val output = CircuitState(inputCircuit, UnknownForm, annos) .resolvePaths(Seq(asdf, lkj)) info(output.circuit.serialize) @@ -582,7 +582,7 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers { val coreModule = ModuleTarget("Top", "Core") val annos = (coreModule +: (relCoreInstances ++ absCoreInstances)).map(DummyAnnotation(_)) val inputCircuit = Parser.parse(input) - val output = CircuitState(passes.ToWorkingIR.run(inputCircuit), UnknownForm, annos) + val output = CircuitState(inputCircuit, UnknownForm, annos) .resolvePaths(relCoreInstances ++ absCoreInstances) info(output.circuit.serialize) diff --git a/src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala b/src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala index 6635026f3..6039d719a 100644 --- a/src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala +++ b/src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala @@ -95,7 +95,6 @@ class MorphismSpec extends AnyFlatSpec with Matchers { val g: Seq[Transform] val setup: Seq[Transform] = Seq( - firrtl2.passes.ToWorkingIR, new firrtl2.ResolveAndCheck ) @@ -167,7 +166,6 @@ class MorphismSpec extends AnyFlatSpec with Matchers { val f: Seq[Transform] val setup: Seq[Transform] = Seq( - firrtl2.passes.ToWorkingIR, new firrtl2.ResolveAndCheck ) diff --git a/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala b/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala index c62a582e8..99636a9f2 100644 --- a/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala +++ b/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala @@ -4,16 +4,12 @@ package firrtlTests.stage import firrtl2.stage._ -import firrtl2.{ir, NoneCompiler, Parser} +import firrtl2.{ir, Parser} import firrtl2.options.Viewer.view import firrtl2.stage.{FirrtlOptions, FirrtlOptionsView} import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers -class BazCompiler extends NoneCompiler - -class Baz_Compiler extends NoneCompiler - class FirrtlOptionsViewSpec extends AnyFlatSpec with Matchers { behavior.of(FirrtlOptionsView.getClass.getName) @@ -28,7 +24,6 @@ class FirrtlOptionsViewSpec extends AnyFlatSpec with Matchers { val annotations = Seq( /* FirrtlOptions */ OutputFileAnnotation("bar"), - CompilerAnnotation(new BazCompiler()), InfoModeAnnotation("use"), FirrtlCircuitAnnotation(grault) ) @@ -49,7 +44,6 @@ class FirrtlOptionsViewSpec extends AnyFlatSpec with Matchers { val overwrites = Seq( OutputFileAnnotation("bar_"), - CompilerAnnotation(new Baz_Compiler()), InfoModeAnnotation("gen"), FirrtlCircuitAnnotation(grault_) ) diff --git a/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala b/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala index 9a9dab24d..efffa9d70 100644 --- a/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala +++ b/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala @@ -41,8 +41,7 @@ class CompilerSpec extends AnyFlatSpec with Matchers { } it should "compile multiple FirrtlCircuitAnnotations" in new Fixture { - val (nc, hfc, mfc, lfc, vc, svc) = ( - new NoneCompiler, + val (hfc, mfc, lfc, vc, svc) = ( new HighFirrtlCompiler, new MiddleFirrtlCompiler, new LowFirrtlCompiler, @@ -63,7 +62,6 @@ class CompilerSpec extends AnyFlatSpec with Matchers { CompilerAnnotation(hfc), /* First compiler group, use NoneCompiler */ FirrtlCircuitAnnotation(Parser.parse(chirrtl("a"))), - CompilerAnnotation(nc), RunFirrtlTransformAnnotation(ce), EmitCircuitAnnotation(ce.getClass), /* Second compiler group, use default HighFirrtlCompiler */ diff --git a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala index 5f3c5ca88..d73713df6 100644 --- a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala +++ b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala @@ -23,7 +23,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec { "CheckWidths on wires with unknown widths" should "result in an error" in { val transforms = - Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths, CheckWidths) + Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths, CheckWidths) val input = """circuit Top : @@ -45,7 +45,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec { "InferWidthsWithAnnos" should "infer widths using WidthGeqConstraintAnnotation" in { val transforms = - Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths, CheckWidths) + Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths, CheckWidths) val annos = Seq( WidthGeqConstraintAnnotation( @@ -84,7 +84,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec { "InferWidthsWithAnnos" should "work with token paths" in { val transforms = - Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths, CheckWidths) + Seq(CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths, CheckWidths) val tokenLists = Seq( Seq(Field("x")), @@ -129,7 +129,6 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec { "InferWidthsWithAnnos" should "work with WiringTransform" in { def transforms() = Seq( - ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows,