From 8c2772e3d18f056a6514e13abff2b1c8319801a6 Mon Sep 17 00:00:00 2001
From: Sylvain Lefebvre <sylvain.lefebvre@inria.fr>
Date: Tue, 3 Dec 2024 12:14:09 +0100
Subject: [PATCH] feature: optim level for easy-riscv, fix: disabling
 printf_chk in classroom

---
 .../soc_wave_player/firmware/Makefile         |  2 +-
 src/RISCVSynthesizer.cpp                      | 28 ++++++++++++++++++-
 src/RISCVSynthesizer.h                        |  2 ++
 3 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/learn-silice/classroom/soc_wave_player/firmware/Makefile b/learn-silice/classroom/soc_wave_player/firmware/Makefile
index 19c26a93..ef7ce9ef 100644
--- a/learn-silice/classroom/soc_wave_player/firmware/Makefile
+++ b/learn-silice/classroom/soc_wave_player/firmware/Makefile
@@ -12,7 +12,7 @@ $(PRGS): %: %.o $(OBJS)
 		$(ARCH)-objdump --disassemble code.elf > code.s
 
 %.o : %.c
-		$(CC) -fno-builtin -fno-unroll-loops $(DEFINES) -Os -fno-stack-protector -fno-pic -march=rv32i -mabi=ilp32 -c $< -o $@
+		$(CC) -U_FORTIFY_SOURCE -fno-builtin -fno-unroll-loops $(DEFINES) -Os -fno-stack-protector -fno-pic -march=rv32i -mabi=ilp32 -c $< -o $@
 
 %.o : %.s
 		$(AS) -march=rv32i -mabi=ilp32 $< -o $@
diff --git a/src/RISCVSynthesizer.cpp b/src/RISCVSynthesizer.cpp
index 6b96879e..206ae682 100644
--- a/src/RISCVSynthesizer.cpp
+++ b/src/RISCVSynthesizer.cpp
@@ -148,6 +148,31 @@ int RISCVSynthesizer::stackSize(siliceParser::RiscvContext *riscv) const
 
 // -------------------------------------------------
 
+std::string RISCVSynthesizer::optimizationLevel(siliceParser::RiscvContext *riscv) const
+{
+  if (riscv->riscvModifiers() != nullptr) {
+    for (auto m : riscv->riscvModifiers()->riscvModifier()) {
+      if (m->IDENTIFIER()->getText() == "O") {
+        if (m->STRING() == nullptr) {
+          if (m->NUMBER() == nullptr) {
+            reportError(sourceloc(riscv), "[RISCV] optimization level should be a number of a string.");
+          } else {
+            return m->NUMBER()->getText();
+          }
+        } else {
+          string level = m->STRING()->getText();
+          level = level.substr(1, level.length() - 2); // remove '"' and '"'
+          return level;
+        }
+      }
+    }
+  }
+  // optional, return default size if not found
+  return "s";
+}
+
+// -------------------------------------------------
+
 std::string RISCVSynthesizer::coreName(siliceParser::RiscvContext *riscv) const
 {
   if (riscv->riscvModifiers() != nullptr) {
@@ -383,6 +408,7 @@ string RISCVSynthesizer::generateSiliceCode(siliceParser::RiscvContext *riscv) c
   code << "$$memsz       = " << memorySize(riscv)/4 << nxl;
   code << "$$external    = " << justHigherPow2(memorySize(riscv))-2 << nxl;
   code << "$$arch        = '" << archName(riscv) << '\'' << nxl;
+  code << "$$O           = '" << optimizationLevel(riscv) << '\'' << nxl;
   code << "$$algorithm_name = '" << riscv->IDENTIFIER()->getText() << "'" << nxl;
   code << "$$dofile('" << normalizePath(CONFIG.keyValues()["libraries_path"]) + "/riscv/riscv-compile.lua')" << nxl;
   code << "$$meminit     = data_bram" << nxl;
@@ -410,7 +436,7 @@ RISCVSynthesizer::RISCVSynthesizer(siliceParser::RiscvContext *riscv)
     // compute stack start
     int stack_start = memorySize(riscv);
     // get stack size
-    int stack_size = stackSize(riscv);
+    int stack_size  = stackSize(riscv);
     // compile from inline source
     siliceParser::CblockContext *cblock = riscv->cblock();
     sl_assert(cblock != nullptr);
diff --git a/src/RISCVSynthesizer.h b/src/RISCVSynthesizer.h
index fc1112b3..58cf5f6b 100644
--- a/src/RISCVSynthesizer.h
+++ b/src/RISCVSynthesizer.h
@@ -64,6 +64,8 @@ namespace Silice
     int         memorySize(siliceParser::RiscvContext *riscv) const;
     /// \brief returns the user-given stack size (if any, 0 otherwise)
     int         stackSize(siliceParser::RiscvContext *riscv) const;
+    /// \brief returns the user-given optimization level
+    std::string optimizationLevel(siliceParser::RiscvContext *riscv) const;
     /// \brief returns the user-given core name (if any, default core selection otherwise)
     std::string coreName(siliceParser::RiscvContext *riscv) const;
     /// \brief returns the user-given architecture variant (defaults to rv32i otherwise)