diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index eed78e4e2..84543dc23 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F03x +# Chip-ID file for STM32F03x device # -chip_id 0x444 -description F03x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x1000 +dev_type STM32F03x +ref_manual_id 0091 +chip_id 0x444 // STM32_CHIPID_F0xx_SMALL +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x1000 // 4 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 1f2a2043e..322e61e51 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F04x +# Chip-ID file for STM32F04x device # -chip_id 0x445 -description F04x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x1800 +dev_type STM32F04x +ref_manual_id 0091 +chip_id 0x445 // STM32_CHIPID_F04 +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x1800 // 6 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index 787adb6bf..3ba9566eb 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F05x +# Chip-ID file for STM32F05x device # -chip_id 0x440 -description F05x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x2000 +dev_type STM32F05x +ref_manual_id 0091 +chip_id 0x440 // STM32_CHIPID_F0 +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x2000 // 8 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index e893a5457..4b1465ca6 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F07x +# Chip-ID file for STM32F07x device # -chip_id 0x448 -description F07x -flash_type 1 -flash_pagesize 0x800 -sram_size 0x4000 +dev_type STM32F07x +ref_manual_id 0091 +chip_id 0x448 // STM32_CHIPID_F0_CAN +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x4000 // 16 KB bootrom_base 0x1fffc800 -bootrom_size 0x3000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x3000 // 12 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 267a2612f..eb6dec428 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -1,13 +1,15 @@ -# Chip-ID file for F09x +# Chip-ID file for STM32F09x device # -chip_id 0x442 -description F09x -flash_type 1 -flash_pagesize 0x800 -sram_size 0x8000 +dev_type STM32F09x +ref_manual_id 0091 +chip_id 0x442 // STM32_CHIPID_F09x +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none diff --git a/config/chips/F1_Low_density_device.chip b/config/chips/F1_Low_density_device.chip deleted file mode 100644 index 33fa03e1b..000000000 --- a/config/chips/F1_Low_density_device.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1 Low-density device -# -chip_id 0x412 -description F1 Low-density device -flash_type 1 -flash_pagesize 0x400 -sram_size 0x2800 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index c2a3b2e69..d774412e1 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -1,13 +1,15 @@ -# Chip-ID file for F1xx CL +# Chip-ID file for STM32F1xx Connectivity Line device # -chip_id 0x418 -description F1xx CL -flash_type 1 -flash_pagesize 0x800 -sram_size 0x10000 +dev_type STM32F1xx_CL +ref_manual_id 0008 +chip_id 0x418 // STM32_CHIPID_F1_CONN +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB bootrom_base 0x1fffb000 -bootrom_size 0x4800 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x4800 // 18 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip new file mode 100644 index 000000000..f454e2a1c --- /dev/null +++ b/config/chips/F1xx_HD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx high density device +# +dev_type F1xx_HD +ref_manual_id 0008 +chip_id 0x414 // STM32_CHIPID_F1_HD +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB +bootrom_base 0x1ffff000 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B +flags swo diff --git a/config/chips/F1xx_High_density.chip b/config/chips/F1xx_High_density.chip deleted file mode 100644 index 1deb5f01b..000000000 --- a/config/chips/F1xx_High_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx High-density -# -chip_id 0x414 -description F1xx High-density -flash_type 1 -flash_pagesize 0x800 -sram_size 0x10000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_High_density_value_line.chip b/config/chips/F1xx_High_density_value_line.chip deleted file mode 100644 index 9e467c9d7..000000000 --- a/config/chips/F1xx_High_density_value_line.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx High-density value line -# -chip_id 0x428 -description F1xx High-density value line -flash_type 1 -flash_pagesize 0x800 -sram_size 0x8000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip new file mode 100644 index 000000000..50f115148 --- /dev/null +++ b/config/chips/F1xx_LD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1 low density device +# +dev_type STM32F1xx_LD +ref_manual_id 0008 +chip_id 0x412 // STM32_CHIPID_F1_LD +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x400 // 1 KB +sram_size 0x2800 // 10 KB +bootrom_base 0x1ffff000 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B +flags swo diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip new file mode 100644 index 000000000..17af311c1 --- /dev/null +++ b/config/chips/F1xx_MD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx medium density device +# +dev_type STM32F1xx_MD +ref_manual_id 0008 +chip_id 0x410 // STM32_CHIPID_F1_MD +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x400 // 1 KB +sram_size 0x5000 // 20 KB +bootrom_base 0x1ffff000 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B +flags swo diff --git a/config/chips/F1xx_Medium_density.chip b/config/chips/F1xx_Medium_density.chip deleted file mode 100644 index a6d81d6f6..000000000 --- a/config/chips/F1xx_Medium_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx Medium-density -# -chip_id 0x410 -description F1xx Medium-density -flash_type 1 -flash_pagesize 0x400 -sram_size 0x5000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip new file mode 100644 index 000000000..c77e013ce --- /dev/null +++ b/config/chips/F1xx_VL_HD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx high density Value Line device +# +dev_type STM32F1xx_VL_HD +ref_manual_id 0041 +chip_id 0x428 // STM32_CHIPID_F1_VL_HD +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB +bootrom_base 0x1ffff000 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B +flags swo diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip new file mode 100644 index 000000000..467fb786f --- /dev/null +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STMF1xx Value Line medium & low density device +# +dev_type STM32F1xx_VL_MD_LD +ref_manual_id 0041 +chip_id 0x420 // STM32_CHIPID_F1_VL_MD_LD +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x400 // 1 KB +sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */ +bootrom_base 0x1ffff000 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B +flags swo diff --git a/config/chips/F1xx_Value_Line.chip b/config/chips/F1xx_Value_Line.chip deleted file mode 100644 index 463cc2d9c..000000000 --- a/config/chips/F1xx_Value_Line.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx Value Line -# -chip_id 0x420 -description F1xx Value Line -flash_type 1 -flash_pagesize 0x400 -sram_size 0x2000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip new file mode 100644 index 000000000..622bd9d02 --- /dev/null +++ b/config/chips/F1xx_XLD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx XL density device +# +dev_type STM32F1xx_XLD +ref_manual_id 0008 +chip_id 0x430 // STM32_CHIPID_F1_XLD +flash_type F1_XL +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x18000 // 96 KB +bootrom_base 0x1fffe000 +bootrom_size 0x1800 // 6 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1xx_XL_density.chip b/config/chips/F1xx_XL_density.chip deleted file mode 100644 index 318efbff0..000000000 --- a/config/chips/F1xx_XL_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx XL-density -# -chip_id 0x430 -description F1xx XL-density -flash_type 2 -flash_pagesize 0x800 -sram_size 0x18000 -bootrom_base 0x1fffe000 -bootrom_size 0x1800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 30808f1aa..30ea174ee 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F2xx +# Chip-ID file for STM32F2xx device # -chip_id 0x411 -description F2xx -flash_type 3 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32F2xx +ref_manual_id 0033 +chip_id 0x411 // STM32_CHIPID_F2 +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x1fffc000 -option_size 0x4 +bootrom_size 0x7800 // 30 KB +option_base 0x1fffc000 // STM32_F2_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index 429c836b4..408f1435e 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F301/F302/F318 +# Chip-ID file for STM32F3xx device (F301x6/8, F302x6x8, F318x8) # -chip_id 0x439 -description F301/F302/F318 -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F301_F302_F318 +ref_manual_id 0365 // also RM0366 +chip_id 0x439 // STM32_CHIPID_F3xx_SMALL +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index ffd1491ff..08c6dc371 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F302/F303/F358 +# Chip-ID file for STM32F3xx device (F302xBxC, F303xB/C, F358) # -chip_id 0x422 -description F302/F303/F358 -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F302_F303_358 +ref_manual_id 0365 // also RM0316 +chip_id 0x422 // STM32_CHIPID_F3 +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip new file mode 100644 index 000000000..7b254c486 --- /dev/null +++ b/config/chips/F302_F303_F398_HD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F3xx high density device (F302xD/E, F303xD/E, F398xE) +# +dev_type STM32F302_F303_F398_HD +ref_manual_id 0365 // also RM0316 (Rev 5) +chip_id 0x446 // STM32_CHIPID_F303_HD +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB +bootrom_base 0x1fffd800 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B +flags swo diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index 5df2a9bbb..daf299cea 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F303/F328/F334 +# Chip-ID file for STM32F3xx device (F303x6/8, F328, F334) # -chip_id 0x438 -description F303/F328/F334 -flash_type 1 -flash_pagesize 0x800 -sram_size 0x3000 +dev_type STM32F303_F328_F334 +ref_manual_id 0364 // also RM0316 +chip_id 0x438 // STM32_CHIPID_F334 +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x3000 // 12 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F303_high_density.chip b/config/chips/F303_high_density.chip deleted file mode 100644 index 748c27cbc..000000000 --- a/config/chips/F303_high_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F303 high density -# -chip_id 0x446 -description F303 high density -flash_type 1 -flash_pagesize 0x800 -sram_size 0x10000 -bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 92201657d..ac249f24f 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F37x +# Chip-ID file for STM32F37x device # -chip_id 0x432 -description F37x -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F37x +ref_manual_id 0313 +chip_id 0x432 // STM32_CHIPID_F37x +flash_type F0_F1_F3 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F401xB_C.chip b/config/chips/F401xB_C.chip deleted file mode 100644 index 09e998dba..000000000 --- a/config/chips/F401xB_C.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F401xB/C -# -chip_id 0x423 -description F401xB/C -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x10000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip new file mode 100644 index 000000000..1022f0fe9 --- /dev/null +++ b/config/chips/F401xB_xC.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F401xB/xC device +# +dev_type STM32F401xB_xC +ref_manual_id 0368 +chip_id 0x423 // STM32_CHIPID_F4_LP +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x10000 // 64 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F401xD_E.chip b/config/chips/F401xD_E.chip deleted file mode 100644 index 5b70d7d86..000000000 --- a/config/chips/F401xD_E.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F401xD/E -# -chip_id 0x433 -description F401xD/E -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x18000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip new file mode 100644 index 000000000..39748a604 --- /dev/null +++ b/config/chips/F401xD_xE.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F401xD/xE device +# +dev_type STM32F401xD_xE +ref_manual_id 0368 +chip_id 0x433 // STM32_CHIPID_F4_DE +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x18000 // 96 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F410.chip b/config/chips/F410.chip index ae199d9c4..5c19450f6 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F410 +# Chip-ID file for STM32F410 device # -chip_id 0x458 -description F410 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x8000 +dev_type STM32F410 +ref_manual_id 0401 +chip_id 0x458 // STM32_CHIPID_F410 +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F411xC_E.chip b/config/chips/F411xC_E.chip deleted file mode 100644 index d344489c5..000000000 --- a/config/chips/F411xC_E.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F411xC/E -# -chip_id 0x431 -description F411xC/E -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x20000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip new file mode 100644 index 000000000..ce93aea26 --- /dev/null +++ b/config/chips/F411xC_xE.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F411xC/xE device +# +dev_type STM32F411xC_xE +ref_manual_id 0383 +chip_id 0x431 // STM32_CHIPID_F411xx +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x20000 // 128 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 3212a340c..a04268349 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F412 +# Chip-ID file for STM32F412 device # -chip_id 0x441 -description F412 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F412 +ref_manual_id 0402 +chip_id 0x441 // STM32_CHIPID_F412 +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index 647775eeb..bb5dd5880 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F413/F423 +# Chip-ID file for STM32F413 / STM32F423 device # -chip_id 0x463 -description F413/F423 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x50000 +dev_type STM32F413_F423 +ref_manual_id 0430 // RM0430 (Rev 2) +chip_id 0x463 // STM32_CHIPID_F413 +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x50000 // 320 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 3184d0d4f..9dc81a120 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F42x/F43x +# Chip-ID file for STM32F42x / STM32F43x device # -chip_id 0x419 -description F42x/F43x -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F42x_F43x +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x419 // STM32_CHIPID_F4_HD +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 86cee6a56..e4d0bdec2 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F446 +# Chip-ID file for STM32F446 device # -chip_id 0x421 -description F446 -flash_type 3 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32F446 +ref_manual_id 0390 +chip_id 0x421 // STM32_CHIPID_F446 +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x1fffc000 -option_size 0x4 +bootrom_size 0x7800 // 30 KB +option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index ee5f6a5a7..f20715ded 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F46x/F47x +# Chip-ID file for STM32F46x / STM32F47x device # -chip_id 0x434 -description F46x/F47x -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F46x_F47x +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x434 // STM32_CHIPID_F4_DSI +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index b19e4a5b3..586ff0b8f 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F4x5/F4x7 +# Chip-ID file for STM32F4x5 / STM32F4x7 device # -chip_id 0x413 -description F4x5/F4x7 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x30000 +dev_type STM32F4x5_F4x7 +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x413 // STM32_CHIPID_F4 +flash_type F2_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x30000 // 192 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x40023c14 -option_size 0x4 +bootrom_size 0x7800 // 30 KB +option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index 2836040ac..04af2bb3e 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F72x/F73x +# Chip-ID file for STM32F72x / STM32F73x device # -chip_id 0x452 -description F72x/F73x -flash_type 3 -flash_pagesize 0x800 -sram_size 0x40000 +dev_type STM32F72x_F73x +ref_manual_id 0431 +chip_id 0x452 // STM32_CHIPID_F72xxx +flash_type F7 +flash_size_reg 0x1ff07a22 +flash_pagesize 0x800 // 2 KB +sram_size 0x40000 // 256 KB bootrom_base 0x100000 -bootrom_size 0xedc0 -option_base 0x0 -option_size 0x0 +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE +option_size 0x20 // 32 B flags swo - diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index 0604b299d..0664bb2d0 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F74x/F75x +# Chip-ID file for STM32F74x / STM32F75x device # -chip_id 0x449 -description F74x/F75x -flash_type 3 -flash_pagesize 0x800 -sram_size 0x50000 +dev_type STM32F74x_F75x +ref_manual_id 0385 +chip_id 0x449 // STM32_CHIPID_F7 +flash_type F7 +flash_size_reg 0x1ff0f442 +flash_pagesize 0x800 // 2 KB +sram_size 0x50000 // 320 KB bootrom_base 0x100000 -bootrom_size 0xedc0 -option_base 0x0 -option_size 0x0 +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE +option_size 0x20 // 32 B flags swo - diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index 304c99191..dfc983254 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F76x/F77x +# Chip-ID file for STM32F76x / STM32F77x device # -chip_id 0x451 -description F76x/F77x -flash_type 4 -flash_pagesize 0x800 -sram_size 0x80000 +dev_type STM32F76x_F77x +ref_manual_id 0410 +chip_id 0x451 // STM32_CHIPID_F76xxx +flash_type F7 +flash_size_reg 0x1ff0f442 +flash_pagesize 0x800 // 2 KB +sram_size 0x80000 // 512 KB bootrom_base 0x200000 -bootrom_size 0xedc0 -option_base 0x1fff0000 -option_size 0x20 -flags dualbank swo - +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE /* Used for reading back option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 */ +option_size 0x20 // 32 B +flags swo dualbank diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index 7c5a00c58..a414b52ab 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G03x/G04x +# Chip-ID file for STM32G030 / STM32G031 / STM32G041 device # -chip_id 0x466 -description G03x/G04x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x2000 +dev_type STM32G03x_G04x +ref_manual_id 0444 // also RM454 +chip_id 0x466 // STM32_CHIPID_G0_CAT1 +flash_type G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x2000 // 8 KB bootrom_base 0x1fff0000 -bootrom_size 0x2000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x2000 // 8 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index 45295ec6e..ae074e584 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G05x/G06x +# Chip-ID file for STM32G05x / STM32G06x device # -chip_id 0x456 -description G05x/G06x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G05x_G06x +ref_manual_id 0444 +chip_id 0x456 // STM32_CHIPID_G0_CAT4 +flash_type G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 7bddcd82c..82b3992c2 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G07x/G08x +# Chip-ID file for STM32G07x / STM32G08x device # -chip_id 0x460 -description G07x/G08x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G07x_G08x +ref_manual_id 0444 +chip_id 0x460 // STM32_CHIPID_G0_CAT2 +flash_type G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index 98e503569..f21fd65a0 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G0Bx/G0Cx +# Chip-ID file for STM32G0Bx / STM32G0Cx device # -chip_id 0x467 -description G0Bx/G0Cx -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G0Bx_G0Cx +ref_manual_id 0444 +chip_id 0x467 // STM32_CHIPID_G0_CAT3 +flash_type G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags dualbank - diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index 033f1dd80..26d1b2f1f 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G43x/G44x +# Chip-ID file for STM32G43x / STM32G44x device # -chip_id 0x468 -description G43x/G44x -flash_type 8 -flash_pagesize 0x800 -sram_size 0x8000 +dev_type STM32G43x_G44x +ref_manual_id 0440 +chip_id 0x468 // STM32_CHIPID_G4_CAT2 +flash_type G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index fa331650f..707727aca 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G47x/G48x +# Chip-ID file for STM32G47x / STM32G48x device # -chip_id 0x469 -description G47x/G48x -flash_type 8 -flash_pagesize 0x800 -sram_size 0x20000 +dev_type STM32G47x_G48x +ref_manual_id 0440 +chip_id 0x469 // STM32_CHIPID_G4_CAT3 +flash_type G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 -flags dualbank swo - +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B +flags swo dualbank diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index b764572db..3e8aacf4b 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G49x/G4Ax +# Chip-ID file for STM32G49x / STM32G4Ax device # -chip_id 0x479 -description G49x/G4Ax -flash_type 8 -flash_pagesize 0x800 -sram_size 0x1c000 +dev_type STM32G49x_G4Ax +ref_manual_id 0440 +chip_id 0x479 // STM32_CHIPID_G4_CAT4 +flash_type G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x1c000 // 112 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index df20037d3..194b740d4 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H72x/H73x +# Chip-ID file for STM32H72x / STM32H73x device # -chip_id 0x483 -description H72x/H73x -flash_type 10 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32H72x_H73x +ref_manual_id 0468 +chip_id 0x483 // STM32_CHIPID_H72x +flash_type H7 +flash_size_reg 0x1ff1e880 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B flags swo - diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 7a4bc86e3..2b829f792 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H74x/H75x +# Chip-ID file for STM32H74x / STM32H75x device # -chip_id 0x450 -description H74x/H75x -flash_type 10 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32H74x_H75x +ref_manual_id 0433 +chip_id 0x450 // STM32_CHIPID_H74xxx +flash_type H7 +flash_size_reg 0x1ff1e880 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c -flags dualbank swo - +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B /* FLASH_OPTSR_CUR to FLASH_BOOT_PRGR */ +flags swo dualbank diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index b9202bd1a..0f66d2c77 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H7Ax/H7Bx +# Chip-ID file for STM32H7Ax / STM32H7Bx device # -chip_id 0x480 -description H7Ax/H7Bx -flash_type 10 -flash_pagesize 0x2000 -sram_size 0x20000 +dev_type STM32H7Ax_H7Bx +ref_manual_id 0455 +chip_id 0x480 // STM32_CHIPID_H7Ax +flash_type H7 +flash_size_reg 0x08fff80c +flash_pagesize 0x2000 // 8 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c -flags dualbank swo - +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B +flags swo dualbank diff --git a/config/chips/L01x_L02x.chip b/config/chips/L01x_L02x.chip deleted file mode 100644 index c3d2074b9..000000000 --- a/config/chips/L01x_L02x.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L01x/L02x -# -chip_id 0x457 -description L01x/L02x -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff00000 -bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 -flags none - diff --git a/config/chips/L0xx_Cat_2.chip b/config/chips/L0xx_Cat_2.chip deleted file mode 100644 index 47183b8ef..000000000 --- a/config/chips/L0xx_Cat_2.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.2 -# -chip_id 0x425 -description L0xx Cat.2 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff0000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x14 -flags none - diff --git a/config/chips/L0xx_Cat_3.chip b/config/chips/L0xx_Cat_3.chip deleted file mode 100644 index 6d9fcc105..000000000 --- a/config/chips/L0xx_Cat_3.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.3 -# -chip_id 0x417 -description L0xx Cat.3 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff0000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x14 -flags none - diff --git a/config/chips/L0xx_Cat_5.chip b/config/chips/L0xx_Cat_5.chip deleted file mode 100644 index 545c1c2ef..000000000 --- a/config/chips/L0xx_Cat_5.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.5 -# -chip_id 0x447 -description L0xx Cat.5 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x5000 -bootrom_base 0x1ff0000 -bootrom_size 0x2000 -option_base 0x1ff80000 -option_size 0x14 -flags dualbank - diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip new file mode 100644 index 000000000..2cce4e23c --- /dev/null +++ b/config/chips/L0xxx_Cat_1.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.1) device (L010x3 / L010x4 / L011x / L021x) +# +dev_type STM32L0xxx_Cat_1 +ref_manual_id 0451 // also RM0377 +chip_id 0x457 // STM32_CHIPID_L011 +flash_type L0_L1 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x2000 // 8 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip new file mode 100644 index 000000000..aae0fac7b --- /dev/null +++ b/config/chips/L0xxx_Cat_2.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.2) device (L010x6 / L031x / L041x) +# +dev_type STM32L0xxx_Cat_2 +ref_manual_id 0451 // also RM0377 +chip_id 0x425 // STM32_CHIPID_L0_CAT2 +flash_type L0_L1 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip new file mode 100644 index 000000000..a04dc8376 --- /dev/null +++ b/config/chips/L0xxx_Cat_3.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.3) device (L010x8 / L051x / L053x / L063x) +# +dev_type STM32L0xxx_Cat_3 +ref_manual_id 0451 // also RM0367 & RM0377 +chip_id 0x417 // STM32_CHIPID_L0 +flash_type L0_L1 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip new file mode 100644 index 000000000..22cbb200a --- /dev/null +++ b/config/chips/L0xxx_Cat_5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.5) device (L010xB / L071x / L081x / L073x / L083x) +# +dev_type STM32L0xxx_Cat_5 +ref_manual_id 0451 // also RM0367 & RM0377 +chip_id 0x447 // STM32_CHIPID_L0_CAT5 +flash_type L0_L1 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x5000 // 20 KB +bootrom_base 0x1ff00000 +bootrom_size 0x2000 // 8 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags dualbank diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index 6c8b211c4..b1b3e85e7 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.1 +# Chip-ID file for STM32L1xx (Cat.1) device (L100C6 / L100R8 / L100RB) # -chip_id 0x416 -description L1xx Cat.1 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x4000 +dev_type STM32L1xx_Cat_1 +ref_manual_id 0038 +chip_id 0x416 // STM32_CHIPID_L1_MD +flash_type L0_L1 +flash_size_reg 0x1ff8004c +flash_pagesize 0x100 // 128 B +sram_size 0x4000 // 16 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index 1ff71edef..695f60d7f 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.2 +# Chip-ID file for STM32L1xx (Cat.2) device (L100C6-A / L100R8-A / L100RB-A) # -chip_id 0x429 -description L1xx Cat.2 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x8000 +dev_type STM32L1xx_Cat_2 +ref_manual_id 0038 +chip_id 0x429 // STM32_CHIPID_L1_CAT2 +flash_type L0_L1 +flash_size_reg 0x1ff8004c +flash_pagesize 0x100 // 128 B +sram_size 0x8000 // 32 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index f417e07f9..43e21f517 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.3 +# Chip-ID file for STM32L1xx (Cat.3) device (L100RC / L15xxC) # -chip_id 0x427 -description L1xx Cat.3 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x8000 +dev_type STM32L1xx_Cat_3 +ref_manual_id 0038 +chip_id 0x427 // STM32_CHIPID_L1_MD_PLUS +flash_type L0_L1 +flash_size_reg 0x1ff800cc +flash_pagesize 0x100 // 128 B +sram_size 0x8000 // 32 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index dbf7869ad..a36118937 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.4 +# Chip-ID file for STM32L1xx (Cat.4) device (L15xxD / L162xD) # -chip_id 0x436 -description L1xx Cat.4 -flash_type 5 -flash_pagesize 0x100 -sram_size 0xc000 +dev_type STM32L1xx_Cat_4 +ref_manual_id 0038 +chip_id 0x436 // STM32_CHIPID_L1_MD_PLUS_HD +flash_type L0_L1 +flash_size_reg 0x1ff800cc +flash_pagesize 0x100 // 128 B +sram_size 0xc000 // 48 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x8 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L1_OPTION_BYTES_BASE +option_size 0x8 // 8 B flags swo - diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index 12342d14f..a487b22bc 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.5 +# Chip-ID file for STM32L1xx (Cat.5) device (L15xxE / L162xE) # -chip_id 0x437 -description L1xx Cat.5 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x14000 +dev_type STM32L1xx_Cat_5 +ref_manual_id 0038 +chip_id 0x437 // STM32_CHIPID_L152_RE +flash_type L0_L1 +flash_size_reg 0x1ff800cc +flash_pagesize 0x100 // 128 B +sram_size 0x14000 // 80 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 3e086e159..11e545bb7 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L41x/L42x +# Chip-ID file for STM32L41x / STM32L42x device # -chip_id 0x464 -description L41x/L42x -flash_type 6 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32L41x_L42x +ref_manual_id 0394 +chip_id 0x464 // STM32_CHIPID_L41x_L42x +flash_type L4_L4P +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 +bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 383c42f3f..f0a959693 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L43x/L44x +# Chip-ID file for STM32L43x / STM32L44x device # -chip_id 0x435 -description L43x/L44x -flash_type 6 -flash_pagesize 0x800 -sram_size 0xc000 +dev_type STM32L41x_L42x +ref_manual_id 0392 +chip_id 0x435 // STM32_CHIPID_L43x_L44x +flash_type L4_L4P +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0xc000 // 48 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/L45x_46x.chip b/config/chips/L45x_46x.chip deleted file mode 100644 index 943b275d5..000000000 --- a/config/chips/L45x_46x.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L45x/46x -# -chip_id 0x462 -description L45x/46x -flash_type 6 -flash_pagesize 0x800 -sram_size 0x20000 -bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip new file mode 100644 index 000000000..267122f87 --- /dev/null +++ b/config/chips/L45x_L46x.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L45x / STM32L46x device +# +dev_type STM32L45x_L46x +ref_manual_id 0394 +chip_id 0x462 // STM32_CHIPID_L45x_L46x +flash_type L4_L4P +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x20000 // 128 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7000 // 28 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 7069229f3..421663e58 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L47x/L48x +# Chip-ID file for STM32L47x / STM32L48x device # -chip_id 0x415 -description L47x/L48x -flash_type 6 -flash_pagesize 0x800 -sram_size 0x18000 +dev_type STM32L47x_L48x +ref_manual_id 0351 +chip_id 0x415 // STM32_CHIPID_L4 +flash_type L4_L4P +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x18000 // 96 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 57f539db3..df1f084ff 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L496x/L4A6x +# Chip-ID file for STM32L496x / STM32L4A6x device # -chip_id 0x461 -description L496x/L4A6x -flash_type 6 -flash_pagesize 0x800 -sram_size 0x40000 +dev_type STM32L496x_L4A6x +ref_manual_id 0351 +chip_id 0x461 // STM32_CHIPID_L496x_L4A6x +flash_type L4_L4P +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index 3e0fbea50..39788eabe 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L4Px +# Chip-ID file for STM32L4Px device # -chip_id 0x471 -description L4Px -flash_type 6 -flash_pagesize 0x1000 -sram_size 0xa0000 +dev_type STM32L4Px +ref_manual_id 0432 +chip_id 0x471 // STM32_CHIPID_L4PX +flash_type L4_L4P +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0xa0000 // 640 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 +bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 -flags dualbank swo - +flags swo diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index a9a26f419..b5c2d0d80 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L4Rx +# Chip-ID file for STM32L4Rx device # -chip_id 0x470 -description L4Rx -flash_type 6 -flash_pagesize 0x1000 -sram_size 0xa0000 +dev_type STM32L4Rx +ref_manual_id 0432 +chip_id 0x470 // STM32_CHIPID_L4RX +flash_type L4_L4P +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0xa0000 // 640 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 +bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 -flags dualbank swo - +flags swo diff --git a/config/chips/L5x5.chip.txt b/config/chips/L5x5.chip.txt new file mode 100644 index 000000000..ce268148b --- /dev/null +++ b/config/chips/L5x5.chip.txt @@ -0,0 +1,15 @@ +# Chip-ID file for STM32L5x2 device +# +dev_type STM32L5x2 +ref_manual_id 0438 +chip_id 0x0 // (temporary setting only!) +flash_type 0 // (temporary setting only!) +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none + diff --git a/config/chips/U5x5.chip.txt b/config/chips/U5x5.chip.txt new file mode 100644 index 000000000..177359cc3 --- /dev/null +++ b/config/chips/U5x5.chip.txt @@ -0,0 +1,15 @@ +# Chip-ID file for STM32U5x5 device +# +dev_type STM32U5x5 +ref_manual_id 0456 +chip_id 0x0 // (temporary setting only!) +flash_type 0 // (temporary setting only!) +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0xc4800 // 786 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none + diff --git a/config/chips/WB5x_3x.chip b/config/chips/WB5x_3x.chip deleted file mode 100644 index 0627bdeec..000000000 --- a/config/chips/WB5x_3x.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for WB5x/3x -# -chip_id 0x495 -description WB5x/3x -flash_type 9 -flash_pagesize 0x1000 -sram_size 0x40000 -bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip new file mode 100644 index 000000000..2747386f8 --- /dev/null +++ b/config/chips/WBx0_WBx5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32WBx0 / STM32WBx5 device +# +dev_type STM32WBx0_WBx5 +ref_manual_id 0434 // also RM0471 +chip_id 0x495 // STM32_CHIPID_WB55 +flash_type WB_WL +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff8000 +option_size 0x80 // 128 B +flags swo diff --git a/config/chips/WLEx.chip b/config/chips/WLEx.chip deleted file mode 100644 index 19d0678e5..000000000 --- a/config/chips/WLEx.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for WLEx -# -chip_id 0x497 -description WLEx -flash_type 9 -flash_pagesize 0x800 -sram_size 0x10000 -bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip new file mode 100644 index 000000000..5bc9d90dc --- /dev/null +++ b/config/chips/WLx5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32WLEx device +# +dev_type STM32WLEx +ref_manual_id 0033 +chip_id 0x497 // STM32_CHIPID_WLE +flash_type WB_WL +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7000 // 28 KB +option_base 0x1fffc000 +option_size 0x10 // 16 B +flags swo diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index c71206951..4eb0c6cbf 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -1,8 +1,10 @@ # Chip-ID file for unknown device # -chip_id 0x0 -description unknown device -flash_type 0 +dev_type unknown +ref_manual_id 0000 +chip_id 0x0 // STM32_CHIPID_UNKNOWN +flash_type UNKNOWN +flash_size_reg 0x0 flash_pagesize 0x0 sram_size 0x0 bootrom_base 0x0 @@ -10,4 +12,3 @@ bootrom_size 0x0 option_base 0x0 option_size 0x0 flags none - diff --git a/doc/devices_boards.md b/doc/devices_boards.md index a8a366448..51b9a0739 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -2,7 +2,7 @@ The following devices are supported by the stlink toolset. -## STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID) +## STM32F0 / ARM Cortex M0 | Chip-ID | Product-Code | | ------- | ------------------- | @@ -19,7 +19,7 @@ The following devices are supported by the stlink toolset. | 0x442 | STM32F0**9**xxx | -## STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID) +## STM32F1 / ARM Cortex M3 | Product-Code | Product Line | | ----------------- | ----------------------- | @@ -45,20 +45,20 @@ Tested non-official ST boards [incl. STLINK programmers]: - HY-STM32 (STM32F103VETx) [v1, v2] - DecaWave EVB1000 (STM32F105RCTx) [v1, v2] -## STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID) +## STM32F2 / ARM Cortex M3 | Chip-ID | Product-Code | Product Line | | ------- | ------------ | ------------- | | 0x411 | STM32F2yyxx | (all devices) | -## STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F1c_CORE_ID) +## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) [may work, but without support!] | Product-Code | Chip-ID | STLink
Programmer | Boards | | ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | | CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
STM32F103C8T6 clone from China Key Systems (CKS) | | CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
STM32F103C8T6 clone from China Key Systems (CKS) | -## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID) +## STM32F3 / ARM Cortex M4F | Product-Code | Product Line | | ----------------- | ------------------------------------------------------------- | @@ -85,13 +85,13 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x446 | _N/A_ | xD xE | | F302 | F303 | | | 0x446 | _N/A_ | - | | | | F398 | -## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID) +## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) [may work, but without support!] | Product-Code | Chip-ID | STLINK
Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | | GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | -## STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID) +## STM32F4 / ARM Cortex M4F | Chip-ID | Product-Code | | ------- | ------------------- | @@ -112,7 +112,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x463 | STM32F4**13**xx | | 0x463 | STM32F4**23**xx | -## STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID) +## STM32F7 / ARM Cortex M7F | Chip-ID | Product-Code | | ------- | --------------- | @@ -123,7 +123,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x451 | STM32F7**6**xxx | | 0x451 | STM32F7**7**xxx | -## STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID) +## STM32H7 / ARM Cortex M7F | Chip-ID | Product-Code | | ------- | ------------- | @@ -132,7 +132,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x480 | STM32H7**A**x | | 0x480 | STM32H7**B**x | -## STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID) +## STM32G0 / ARM Cortex M0+ | Chip-ID | Product-Code | | ------- | --------------- | @@ -141,7 +141,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x460 | STM32G0**7**xxx | | 0x460 | STM32G0**8**xxx | -## STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID) +## STM32G4 / ARM Cortex M4F | Chip-ID | Product-Code | | ------- | --------------- | @@ -151,7 +151,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x469 | STM32G4**8**xxx | | 0x479 | STM32G4**91**xx | -## STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID) +## STM32L0 / ARM Cortex M0+ | Chip-ID | Product-Code | | ------- | --------------- | @@ -164,7 +164,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x447 | STM32L0**7**xxx | | 0x447 | STM32L0**8**xxx | -## STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID) +## STM32L1 / ARM Cortex M3 | Chip-ID | Product-Code | | ------- | ---------------- | @@ -178,7 +178,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x436 | STM32L1xxx**D** | | 0x437 | STM32L1xxx**E** | -## STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID) +## STM32L4 / ARM Cortex M4F | Chip-ID | Product-Code | | ------- | --------------- | @@ -197,7 +197,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x471 | STM32L4**P5**xx | | 0x471 | STM32L4**Q5**xx | -## STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID) +## STM32W / ARM Cortex M3 | Chip-ID | Product-Code | | ------- | --------------- | diff --git a/doc/tutorial.md b/doc/tutorial.md index 955f85611..9ca6bef5b 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -81,7 +81,7 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output. -Make sure that you have all 4 files from here: https://github.com/stlink-org/stlink/tree/master/config/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: +Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing existing files in `/etc/udev/ruled.d` you should run the following: ``` sudo udevadm control --reload-rules diff --git a/inc/stlink.h b/inc/stlink.h index df13aa7c9..2d0fa5007 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,6 +83,10 @@ enum target_state { #define STLINK_F_HAS_DPBANKSEL (1 << 8) #define STLINK_F_HAS_RW8_512BYTES (1 << 9) +/* Additional MCU features */ +#define CHIP_F_HAS_DUAL_BANK (1 << 0) +#define CHIP_F_HAS_SWO_TRACING (1 << 1) + /* Error code */ #define STLINK_DEBUG_ERR_OK 0x80 #define STLINK_DEBUG_ERR_FAULT 0x81 @@ -102,21 +106,6 @@ enum target_state { #define C_BUF_LEN 32 -enum stlink_flash_type { - STLINK_FLASH_TYPE_UNKNOWN = 0, - STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ - STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank, apparently */ - STLINK_FLASH_TYPE_F4, // used by f2, f4 */ - STLINK_FLASH_TYPE_F7, - STLINK_FLASH_TYPE_L0, // l0, l1 */ - STLINK_FLASH_TYPE_L4, // l4, l4+ */ - STLINK_FLASH_TYPE_G0, - STLINK_FLASH_TYPE_G4, - STLINK_FLASH_TYPE_WB, - STLINK_FLASH_TYPE_H7, - STLINK_FLASH_TYPE_MAX, -}; - struct stlink_reg { uint32_t r[16]; uint32_t s[32]; @@ -194,6 +183,7 @@ enum run_type { typedef struct _stlink stlink_t; +#include #include struct _stlink { @@ -216,8 +206,8 @@ struct _stlink { char serial[STLINK_SERIAL_BUFFER_SIZE]; int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR - enum stlink_flash_type flash_type; - // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx + enum stm32_flash_type flash_type; + // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() size_t flash_size; // calculated by stlink_load_device_params() diff --git a/inc/stm32.h b/inc/stm32.h index 21da2f563..d6bbe506c 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -1,38 +1,535 @@ /* * File: stm32.h * - * STM32-specific defines + * STM32-specific defines & identification parametres */ #ifndef STM32_H #define STM32_H -/* Cortex core ids */ -#define STM32VL_CORE_ID 0x1ba01477 -#define STM32F7_CORE_ID 0x5ba02477 -#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code -#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065) - -/* Constant STM32 memory map figures */ -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) - -#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) -#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14) -#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) -#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) - -#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) -#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) - -#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) -#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) - -#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +/* STM32 Cortex-M core ids (CPUTAPID) */ +enum stm32_core_id { + STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP + // (RM0444 Section 40.5.3) G0 SW-DP + STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP + STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP + STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG + STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP + // (RM0038 Section 30.8.3) L1 SW-DP + STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG + // (RM0038 Section 30.6.2) L1 JTAG + STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP + // (RM0351 Section 48.8.3) L4 SW-DP + // (RM0432 Section 57.8.3) L4+ SW-DP + STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG + // (RM0351 Section 48.6.3) L4 JTAG + // (RM0432 Section 57.6.3) L4+ JTAG + STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP + // (RM0090 Section 47.8.3) G4 SW-DP + STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG + // (RM0090 Section 47.6.3) G4 JTAG + STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP + STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG + STM32_CORE_ID_M7F_H7_SWD = 0x6ba02477, // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M7F_H7_JTAG = 0x6ba00477, // (RM0433 Section 60.4.1) H7 JTAG + STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP + // (RM0456 Section 65.3.3) U5 SW-DP + STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP + // (RM0456 Section 65.3.3) U5 JTAG-DP + STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG + // (RM0456 Section 56.3.1) U5 JTAG +}; + +/* STM32 flash types */ +enum stm32_flash_type { + STM32_FLASH_TYPE_UNKNOWN = 0, + STM32_FLASH_TYPE_F0_F1_F3 = 1, + STM32_FLASH_TYPE_F1_XL = 2, + STM32_FLASH_TYPE_F2_F4 = 3, + STM32_FLASH_TYPE_F7 = 4, + STM32_FLASH_TYPE_G0 = 5, + STM32_FLASH_TYPE_G4 = 6, + STM32_FLASH_TYPE_H7 = 7, + STM32_FLASH_TYPE_L0_L1 = 8, + STM32_FLASH_TYPE_L4_L4P = 9, + STM32_FLASH_TYPE_L5_U5 = 10, + STM32_FLASH_TYPE_WB_WL = 11, +}; + +/* STM32 chip-ids */ +// See DBGMCU_IDCODE register (0xE0042000) in appropriate programming manual +// stm32 chipids, only lower 12 bits... + +enum stm32_chipids { + STM32_CHIPID_UNKNOWN = 0x000, + + STM32_CHIPID_F1_MD = 0x410, /* medium density */ + STM32_CHIPID_F2 = 0x411, + STM32_CHIPID_F1_LD = 0x412, /* low density */ + STM32_CHIPID_F4 = 0x413, + STM32_CHIPID_F1_HD = 0x414, /* high density */ + STM32_CHIPID_L4 = 0x415, + STM32_CHIPID_L1_MD = 0x416, /* medium density */ + STM32_CHIPID_L0 = 0x417, + STM32_CHIPID_F1_CONN = 0x418, /* connectivity line */ + STM32_CHIPID_F4_HD = 0x419, /* high density */ + STM32_CHIPID_F1_VL_MD_LD = 0x420, /* value line medium & low density */ + STM32_CHIPID_F446 = 0x421, + STM32_CHIPID_F3 = 0x422, + STM32_CHIPID_F4_LP = 0x423, + STM32_CHIPID_L0_CAT2 = 0x425, + STM32_CHIPID_L1_MD_PLUS = 0x427, /* medium density plus */ + STM32_CHIPID_F1_VL_HD = 0x428, /* value line high density */ + STM32_CHIPID_L1_CAT2 = 0x429, + STM32_CHIPID_F1_XLD = 0x430, /* extra low density plus */ + STM32_CHIPID_F411xx = 0x431, + STM32_CHIPID_F37x = 0x432, + STM32_CHIPID_F4_DE = 0x433, + STM32_CHIPID_F4_DSI = 0x434, + STM32_CHIPID_L43x_L44x = 0x435, + STM32_CHIPID_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ + STM32_CHIPID_L152_RE = 0x437, + STM32_CHIPID_F334 = 0x438, + STM32_CHIPID_F3xx_SMALL = 0x439, + STM32_CHIPID_F0 = 0x440, + STM32_CHIPID_F412 = 0x441, + STM32_CHIPID_F09x = 0x442, + STM32_CHIPID_F0xx_SMALL = 0x444, + STM32_CHIPID_F04 = 0x445, + STM32_CHIPID_F303_HD = 0x446, /* high density */ + STM32_CHIPID_L0_CAT5 = 0x447, + STM32_CHIPID_F0_CAN = 0x448, + STM32_CHIPID_F7 = 0x449, /* Nucleo F746ZG board */ + STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ + STM32_CHIPID_F76xxx = 0x451, + STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ + STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ + STM32_CHIPID_L011 = 0x457, + STM32_CHIPID_F410 = 0x458, + STM32_CHIPID_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STM32_CHIPID_L496x_L4A6x = 0x461, + STM32_CHIPID_L45x_L46x = 0x462, + STM32_CHIPID_F413 = 0x463, + STM32_CHIPID_L41x_L42x = 0x464, + STM32_CHIPID_G0_CAT1 = 0x466, /* G030/G031/G041 */ + STM32_CHIPID_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STM32_CHIPID_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ + STM32_CHIPID_G4_CAT3 = 0x469, + STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ + STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */ + STM32_CHIPID_G4_CAT4 = 0x479, + STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ + STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ + STM32_CHIPID_WB55 = 0x495, + STM32_CHIPID_WLE = 0x497, +}; + +/* Constant STM32 option bytes base memory address */ +#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) + +#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) + +#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1ff80000) +#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1ff80000) + +#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1fff0000) + +#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) +#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) + +#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1fffc000) + +#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) + +/* ============ */ +/* Old defines from common.c are below */ +/* ============ */ + +/* Constant STM32 memory address */ +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) + +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) + +/* stm32f FPEC flash controller interface, pm0063 manual */ +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) +#define FLASH_REGS_ADDR 0x40022000 +#define FLASH_REGS_SIZE 0x28 + +#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) +#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) +#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) +#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) +#define FLASH_CR (FLASH_REGS_ADDR + 0x10) +#define FLASH_AR (FLASH_REGS_ADDR + 0x14) +#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) +#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) + +// STM32F10x_XL has two flash memory banks with separate registers to control +// the second bank. +#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) +#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) +#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) +#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) + +// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... +#define FLASH_RDPTR_KEY 0x00a5 +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xcdef89ab + +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 + +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 + +#define FLASH_OPTKEY1 0x08192A3B +#define FLASH_OPTKEY2 0x4C5D6E7F + +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xCDEF89AB + +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 + +#define FLASH_SR_BSY 0 +#define FLASH_SR_PG_ERR 2 +#define FLASH_SR_WRPRT_ERR 4 +#define FLASH_SR_EOP 5 + +#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) + +#define FLASH_CR_PG 0 +#define FLASH_CR_PER 1 +#define FLASH_CR_MER 2 +#define FLASH_CR_OPTPG 4 +#define FLASH_CR_OPTER 5 +#define FLASH_CR_STRT 6 +#define FLASH_CR_LOCK 7 +#define FLASH_CR_OPTWRE 9 +#define FLASH_CR_OBL_LAUNCH 13 + +#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) +#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) +#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) +#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) +#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) +#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) +#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) +#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) +#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 + +// Flash registers common to STM32G0 and STM32G4 series. +#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) +#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) +#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) +#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) +#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) +#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) +#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) + +// G0 (RM0444 Table 1, sec 3.7) +// Mostly the same as G4 chips, but the notation +// varies a bit after the 'OPTR' register. +#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) +#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) +#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) +#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) +#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) +#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) +#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) + +// G4 (RM0440 Table 17, sec 3.7.19) +// Mostly the same as STM32G0 chips, but there are a few extra +// registers because 'cat 3' devices can have two Flash banks. +#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) +#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) +#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) +#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) +#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) +#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) +#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) +#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) +#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) +#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) +#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) + +// G0/G4 FLASH control register +#define STM32Gx_FLASH_CR_PG (0) /* Program */ +#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ +#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ +#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ +#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define STM32Gx_FLASH_CR_STRT (16) /* Start */ +#define STM32Gx_FLASH_CR_OPTSTRT \ + (17) /* Start of modification of option bytes */ +#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ +#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ +#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ +#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ +#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ + +// G0/G4 FLASH status register +#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) +#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ + +// G4 FLASH option register +#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ + +// WB (RM0434) +#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) +#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) +#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) + +// WB Flash control register. +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +// WB Flash status register. +#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ + +// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 +#define STM32L4_FLASH_SR_BSY 16 + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ + (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) +// Page is fully specified by BKER and PNB +#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) + +#define STM32L4_FLASH_OPTR_DUALBANK 21 + +// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf +#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) + +#define STM32L0_FLASH_PELOCK (0) +#define STM32L0_FLASH_OPTLOCK (2) +#define STM32L0_FLASH_OBL_LAUNCH (18) + +#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_NOTZEROERR 16 + +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// STM32F7 +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) + +// STM32F4 +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0xf8 +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 + +// STM32F2 +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 + +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 +#define FLASH_F2_SR_BSY 16 + +// STM32H7xx +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 + +#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) + +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 + +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 + +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 + +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) + +#define STM32F0_DBGMCU_CR 0xE0042004 +#define STM32F0_DBGMCU_CR_IWDG_STOP 8 +#define STM32F0_DBGMCU_CR_WWDG_STOP 9 + +#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 +#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32L0_DBGMCU_APB1_FZ 0x40015808 +#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 + +#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 +#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 + +#define STM32WB_DBGMCU_APB1FZR1 0xE004203C +#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32F1_RCC_AHBENR 0x40021014 +#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32F4_RCC_AHB1ENR 0x40023830 +#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN + +#define STM32G0_RCC_AHBENR 0x40021038 +#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32G4_RCC_AHB1ENR 0x40021048 +#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32L0_RCC_AHBENR 0x40021030 +#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN + +#define STM32H7_RCC_AHB1ENR 0x58024538 +#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32WB_RCC_AHB1ENR 0x58000048 +#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define L1_WRITE_BLOCK_SIZE 0x80 +#define L0_WRITE_BLOCK_SIZE 0x40 #endif // STM32_H diff --git a/src/common.c b/src/common.c index 6cbd217ef..266722b91 100644 --- a/src/common.c +++ b/src/common.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #ifdef STLINK_HAVE_SYS_MMAN_H @@ -34,384 +35,7 @@ #define BANK_1 0 #define BANK_2 1 -/* stm32f FPEC flash controller interface, pm0063 manual */ -// TODO - all of this needs to be abstracted out.... -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, -// August 2012) -#define FLASH_REGS_ADDR 0x40022000 -#define FLASH_REGS_SIZE 0x28 - -#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) -#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) -#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) -#define FLASH_CR (FLASH_REGS_ADDR + 0x10) -#define FLASH_AR (FLASH_REGS_ADDR + 0x14) -#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) -#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) - -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. -#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) -#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) -#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) -#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) - -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... -#define FLASH_RDPTR_KEY 0x00a5 -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab - -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 - -#define FLASH_SR_BSY 0 -#define FLASH_SR_PG_ERR 2 -#define FLASH_SR_WRPRT_ERR 4 -#define FLASH_SR_EOP 5 - -#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) - -#define FLASH_CR_PG 0 -#define FLASH_CR_PER 1 -#define FLASH_CR_MER 2 -#define FLASH_CR_OPTPG 4 -#define FLASH_CR_OPTER 5 -#define FLASH_CR_STRT 6 -#define FLASH_CR_LOCK 7 -#define FLASH_CR_OPTWRE 9 -#define FLASH_CR_OBL_LAUNCH 13 - -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 - -// Flash registers common to STM32G0 and STM32G4 series. -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) - -// G0 (RM0444 Table 1, sec 3.7) -// Mostly the same as G4 chips, but the notation -// varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) - -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) - -// G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ - -// G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ - -// G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ - -// WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) - -// WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ - -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ -// Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) -// Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) - -#define STM32L4_FLASH_OPTR_DUALBANK 21 - -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) - -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) - -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 - -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 - -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) - -#define STM32F0_DBGMCU_CR 0xE0042004 -#define STM32F0_DBGMCU_CR_IWDG_STOP 8 -#define STM32F0_DBGMCU_CR_WWDG_STOP 9 - -#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 -#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32L0_DBGMCU_APB1_FZ 0x40015808 -#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 -#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 - -#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 -#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 - -#define STM32WB_DBGMCU_APB1FZR1 0xE004203C -#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32F1_RCC_AHBENR 0x40021014 -#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32F4_RCC_AHB1ENR 0x40023830 -#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN - -#define STM32G0_RCC_AHBENR 0x40021038 -#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32G4_RCC_AHB1ENR 0x40021048 -#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32L0_RCC_AHBENR 0x40021030 -#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN - -#define STM32H7_RCC_AHB1ENR 0x58024538 -#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32WB_RCC_AHB1ENR 0x58000048 -#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define L1_WRITE_BLOCK_SIZE 0x80 -#define L0_WRITE_BLOCK_SIZE 0x40 + // Endianness // https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html @@ -440,16 +64,16 @@ uint16_t read_uint16(const unsigned char *c, const int pt) { static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L0: - case STLINK_CHIPID_STM32_L0_CAT5: - case STLINK_CHIPID_STM32_L0_CAT2: - case STLINK_CHIPID_STM32_L011: + case STM32_CHIPID_L0: + case STM32_CHIPID_L0_CAT5: + case STM32_CHIPID_L0_CAT2: + case STM32_CHIPID_L011: return (STM32L0_FLASH_REGS_ADDR); - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MD: - case STLINK_CHIPID_STM32_L1_MD_PLUS: - case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: + case STM32_CHIPID_L1_CAT2: + case STM32_CHIPID_L1_MD: + case STM32_CHIPID_L1_MD_PLUS: + case STM32_CHIPID_L1_MD_PLUS_HD: return (STM32L_FLASH_REGS_ADDR); default: @@ -467,18 +91,18 @@ static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { uint32_t reg, res; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; } else { reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -498,30 +122,30 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { uint32_t cr_reg; uint32_t n; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; cr_lock_shift = FLASH_H7_CR_LOCK; } else { @@ -542,27 +166,27 @@ static void unlock_flash(stlink_t *sl) { * definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { key_reg = FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { key_reg = FLASH_KEYR; key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; flash_key1 = FLASH_L0_PEKEY1; flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { key2_reg = FLASH_H7_KEYR2; @@ -600,33 +224,33 @@ static void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { cr_reg = FLASH_CR; cr2_reg = FLASH_CR2; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; @@ -655,38 +279,38 @@ static bool is_flash_option_locked(stlink_t *sl) { uint32_t n; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; optlock_shift = FLASH_CR_OPTWRE; active_bit_level = 0; /* bit is "option write enable", not lock */ break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optcr_reg = STM32Gx_FLASH_CR; optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; break; @@ -709,38 +333,38 @@ static int lock_flash_option(stlink_t *sl) { int active_bit_level = 1; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; optlock_shift = FLASH_CR_OPTWRE; active_bit_level = 0; break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optcr_reg = STM32Gx_FLASH_CR; optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) @@ -782,34 +406,34 @@ static int unlock_flash_option(stlink_t *sl) { uint32_t optkey2 = FLASH_OPTKEY2; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optkey_reg = FLASH_OPTKEYR; optkey1 = FLASH_F0_OPTKEY1; optkey2 = FLASH_F0_OPTKEY2; break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optkey_reg = FLASH_F4_OPT_KEYR; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optkey_reg = FLASH_F7_OPT_KEYR; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; optkey1 = FLASH_L0_OPTKEY1; optkey2 = FLASH_L0_OPTKEY2; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optkey_reg = STM32L4_FLASH_OPTKEYR; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optkey_reg = STM32Gx_FLASH_OPTKEYR; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optkey_reg = STM32WB_FLASH_OPT_KEYR; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) optkey2_reg = FLASH_H7_OPT_KEYR2; @@ -852,24 +476,24 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; x |= (1 << FLASH_H7_CR_PG); } else { @@ -884,18 +508,18 @@ static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { uint32_t cr_reg, n; uint32_t bit = FLASH_CR_PG; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; bit = FLASH_H7_CR_PG; } else { @@ -909,10 +533,10 @@ static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { static void set_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg, val; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -926,10 +550,10 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -942,20 +566,20 @@ static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { uint32_t val, cr_reg, cr_mer, cr_pg; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); @@ -964,11 +588,11 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { } cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_mer = (1 << FLASH_H7_CR_BER); cr_pg = (1 << FLASH_H7_CR_PG); @@ -998,23 +622,23 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { uint32_t val, cr_reg, cr_strt; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); } else { @@ -1030,23 +654,23 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { uint32_t res, sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else { ELOG("method 'read_flash_sr' is unsupported\n"); @@ -1060,23 +684,23 @@ static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { uint32_t sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else { ELOG("method 'write_flash_sr' is unsupported\n"); @@ -1090,22 +714,22 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { ELOG("method 'is_flash_busy' is unsupported\n"); @@ -1114,8 +738,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); } @@ -1149,32 +773,32 @@ static void wait_flash_busy_progress(stlink_t *sl) { static void clear_flash_error(stlink_t *sl) { switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: + case STM32_FLASH_TYPE_F0_F1_F3: write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); } break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); break; default: @@ -1189,52 +813,52 @@ static int check_flash_error(stlink_t *sl) { WRPERR = PROGERR = PGAERR = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; } WRPERR = (1 << FLASH_SR_WRPRT_ERR); PROGERR = (1 << FLASH_SR_PG_ERR); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; WRPERR = (1 << FLASH_F4_SR_WRPERR); PGAERR = (1 << FLASH_F4_SR_PGAERR); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; WRPERR = (1 << FLASH_F7_SR_WRP_ERR); PROGERR = (1 << FLASH_F7_SR_PGP_ERR); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; } WRPERR = (1 << FLASH_H7_SR_WRPERR); break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); @@ -1271,31 +895,31 @@ static void stop_wdg_in_debug(stlink_t *sl) { uint32_t value; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_G4: dbgmcu_cr = STM32F0_DBGMCU_CR; set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_L4_L4P: dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); break; - case STLINK_FLASH_TYPE_L0: - case STLINK_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_L0_L1: + case STM32_FLASH_TYPE_G0: dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); @@ -1315,34 +939,34 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc = rcc_dma_mask = value = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: rcc = STM32F1_RCC_AHBENR; rcc_dma_mask = STM32F1_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: rcc = STM32F4_RCC_AHB1ENR; rcc_dma_mask = STM32F4_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G0: rcc = STM32G0_RCC_AHBENR; rcc_dma_mask = STM32G0_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_G4: - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_L4_L4P: rcc = STM32G4_RCC_AHB1ENR; rcc_dma_mask = STM32G4_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: rcc = STM32L0_RCC_AHBENR; rcc_dma_mask = STM32L0_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: rcc = STM32H7_RCC_AHB1ENR; rcc_dma_mask = STM32H7_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: rcc = STM32WB_RCC_AHB1ENR; rcc_dma_mask = STM32WB_RCC_DMAEN; break; @@ -1370,7 +994,7 @@ static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, uint32_t cr_reg, psize_shift; uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; psize_shift = FLASH_H7_CR_PSIZE; } else { @@ -1390,7 +1014,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { uint32_t cr_reg, snb_mask, snb_shift, ser_shift; uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; snb_mask = FLASH_H7_CR_SNB_MASK; snb_shift = FLASH_H7_CR_SNB; @@ -1443,7 +1067,7 @@ void stlink_close(stlink_t *sl) { int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); - if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && + if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN && sl->core_stat != TARGET_RESET) { // stop debugging if the target has been identified stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); @@ -1513,7 +1137,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * */ - if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && + if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); @@ -1604,7 +1228,7 @@ int stlink_load_device_params(stlink_t *sl) { return (-1); } - if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + if (params->flash_type == STM32_FLASH_TYPE_UNKNOWN) { WLOG("Invalid flash type, please check device declaration\n"); sl->flash_size = 0; return (0); @@ -1621,14 +1245,14 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && + if ((sl->chip_id == STM32_CHIPID_L1_MD || + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) { // 0 is 384k and 1 is 256k if (flash_size == 0) { sl->flash_size = 384 * 1024; @@ -1650,12 +1274,12 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } - if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { + if (sl->chip_id == STM32_CHIPID_G4_CAT3) { uint32_t flash_optr; stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); @@ -1666,13 +1290,13 @@ int stlink_load_device_params(stlink_t *sl) { // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && - sl->flash_type == STLINK_FLASH_TYPE_H7) { + sl->flash_type == STM32_FLASH_TYPE_H7) { if ((sl->flash_size / sl->flash_pgsz) <= 1) sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->description, (unsigned)(sl->sram_size / 1024), + params->dev_type, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), @@ -2705,9 +2329,9 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; - if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || - sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { + if (sl->chip_id == STM32_CHIPID_L4 || + sl->chip_id == STM32_CHIPID_L496x_L4A6x || + sl->chip_id == STM32_CHIPID_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; @@ -2725,16 +2349,16 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || - (sl->chip_id == STLINK_CHIPID_STM32_F4) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + if ((sl->chip_id == STM32_CHIPID_F2) || + (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || + (sl->chip_id == STM32_CHIPID_F4_HD) || + (sl->chip_id == STM32_CHIPID_F411xx) || + (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_F4_DSI) || + (sl->chip_id == STM32_CHIPID_F72xxx) || + (sl->chip_id == STM32_CHIPID_F412)) { uint32_t sector = calculate_F4_sectornum(flashaddr); if (sector >= 12) { @@ -2748,8 +2372,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } else { sl->flash_pgsz = 0x20000; } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { @@ -2777,18 +2401,18 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // clear flash IO errors clear_flash_error(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || + sl->flash_type == STM32_FLASH_TYPE_F7 || + sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { // unlock if locked unlock_flash_if(sl); // select the page to erase - if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || - (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { + if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || + (sl->chip_id == STM32_CHIPID_L4Rx)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -2796,8 +2420,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); @@ -2826,7 +2450,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); #endif - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); @@ -2882,15 +2506,15 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit // set the page to erase - if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); @@ -2900,7 +2524,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val |= ((flash_page & 0xFF) << 3); stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -2908,7 +2532,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x3F << 3); val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -2922,8 +2546,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { wait_flash_busy(sl); // wait for the 'busy' bit to clear clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); clear_flash_cr_pg(sl, bank); // clear the pg bit @@ -2934,7 +2558,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { wait_flash_busy(sl); clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); // unlock if locked uint32_t sector = calculate_H7_sectornum( @@ -3021,8 +2645,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { int err = 0; // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); @@ -3031,8 +2655,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { clear_flash_error(sl); unlock_flash_if(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + if (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -3044,8 +2668,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { set_flash_cr_strt( sl, BANK_1); // start erase operation, reset by hw with busy bit - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 @@ -3056,8 +2680,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { // reset the mass erase bit set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 0, BANK_2); } @@ -3194,9 +2818,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // Clear errors clear_flash_error(sl); - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { ILOG("Starting Flash write for F2/F4/F7/L4\n"); // Flash loader initialisation @@ -3220,7 +2844,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (-1); } - if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { // L4 does not have a byte-write mode if (voltage < 1710) { ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); @@ -3240,14 +2864,14 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // set programming mode set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { ILOG("Starting Flash write for WB/G0/G4\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { ILOG("Starting Flash write for L0\n"); uint32_t val; @@ -3284,8 +2908,8 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // L0/L1 have fallback to soft write WLOG("stlink_flash_loader_init() == -1\n"); } - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); // flash loader initialisation @@ -3299,10 +2923,10 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // set programming mode set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl, BANK_2); } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { ILOG("Starting Flash write for H7\n"); unlock_flash_if(sl); // unlock the cr @@ -3310,7 +2934,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } - if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + if (sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -3328,9 +2952,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { size_t off; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; @@ -3344,9 +2968,9 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, off += size; } - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; @@ -3370,7 +2994,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, 0); // write a single word of zeros wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? @@ -3410,8 +3034,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, // TODO: check redo write operation } fprintf(stdout, "\n"); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { int write_block_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size @@ -3443,7 +3067,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (sl->verbose >= 1) { fprintf(stdout, "\n"); } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { for (off = 0; off < len;) { // Program STM32H7x with 64-byte Flash words size_t chunk = (len - off > 64) ? 64 : len - off; @@ -3473,24 +3097,24 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4) || - (sl->flash_type == STLINK_FLASH_TYPE_WB) || - (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || - (sl->flash_type == STLINK_FLASH_TYPE_H7)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || + (sl->flash_type == STM32_FLASH_TYPE_G0) || + (sl->flash_type == STM32_FLASH_TYPE_G4) || + (sl->flash_type == STM32_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { clear_flash_cr_pg(sl, BANK_2); } lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); @@ -3745,7 +3369,7 @@ int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, } uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { return (0x00); } else { return (0xff); @@ -4385,17 +4009,17 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: + case STM32_CHIPID_F2: return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F446: + case STM32_CHIPID_F4: + case STM32_CHIPID_F446: return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F76xxx: + case STM32_CHIPID_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: + case STM32_CHIPID_G0_CAT1: + case STM32_CHIPID_G0_CAT2: + case STM32_CHIPID_G4_CAT2: + case STM32_CHIPID_G4_CAT3: return stlink_read_option_bytes_Gx(sl, option_byte); default: return stlink_read_option_bytes_generic(sl, option_byte); @@ -4416,7 +4040,7 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_bytes_boot_add_f7(sl, option_byte); default: return -1; @@ -4437,10 +4061,10 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: return stlink_read_option_control_register_f0(sl, option_byte); - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register_f7(sl, option_byte); default: return -1; @@ -4461,7 +4085,7 @@ int stlink_read_option_control_register1_32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register1_f7(sl, option_byte); default: return -1; @@ -4523,27 +4147,27 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_bytes_f0(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: ret = stlink_write_option_bytes_f4(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_bytes_f7(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: ret = stlink_write_option_bytes_l0(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: ret = stlink_write_option_bytes_l4(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: ret = stlink_write_option_bytes_gx(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: ret = stlink_write_option_bytes_h7(sl, base, addr, len); break; default: @@ -4761,7 +4385,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); break; default: @@ -4806,11 +4430,11 @@ int stlink_write_option_control_register32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_control_register_f0(sl, option_control_register); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register_f7(sl, option_control_register); break; default: @@ -4855,7 +4479,7 @@ int stlink_write_option_control_register1_32( } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register1_f7(sl, option_control_register1); break; diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 6ac2ba48b..a9952dd34 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -8,6 +8,7 @@ #include #include +#include #include #include "flash.h" @@ -67,7 +68,7 @@ int main(int ac, char** av) { if (sl == NULL) { return(-1); } - if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + if (sl->flash_type == STM32_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); goto on_error; } diff --git a/src/st-info/info.c b/src/st-info/info.c index ceb406cda..618046ddd 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -33,16 +33,14 @@ static void stlink_print_info(stlink_t *sl) { if (!sl) { return; } - printf(" version: "); - stlink_print_version(sl); + printf(" version: "); stlink_print_version(sl); printf(" serial: %s\n", sl->serial); - printf(" flash: %u (pagesize: %u)\n", - (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); + printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); printf(" sram: %u\n", (uint32_t)sl->sram_size); - printf(" chipid: 0x%.4x\n", sl->chip_id); + printf(" chipid: 0x%.3x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); - if (params) { printf(" descr: %s\n", params->description); } + if (params) { printf(" dev-type: %s\n", params->dev_type); } } static void stlink_probe(enum connect_type connect, int freq) { @@ -118,7 +116,7 @@ static int print_data(int ac, char **av) { const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); if (params == NULL) { return(-1); } - printf("%s\n", params->description); + printf("%s\n", params->dev_type); } if (sl) { diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 754a55c72..28a585071 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -540,7 +540,7 @@ int main(int argc, char **argv) { stlink->verbose = settings.logging_level; - if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { + if (stlink->chip_id == STM32_CHIPID_UNKNOWN) { ELOG("Your stlink is not connected to a device\n"); if (!settings.force) return APP_RESULT_STLINK_MISSING_DEVICE; @@ -555,7 +555,7 @@ int main(int argc, char **argv) { if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'\n", params->description); + ELOG("We do not support SWO output for device '%s'\n", params->dev_type); if (!settings.force) return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 81c0aa83a..4f7a1fe2e 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -226,7 +226,7 @@ int main(int argc, char** argv) { sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); if (sl == NULL) { return(1); } - if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { + if (sl->chip_id == STM32_CHIPID_UNKNOWN) { ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id); return(1); } @@ -553,39 +553,39 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(sz); map[0] = '\0'; - if (sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F446 || - sl->chip_id == STLINK_CHIPID_STM32_F411xx) { + if (sl->chip_id == STM32_CHIPID_F4 || + sl->chip_id == STM32_CHIPID_F446 || + sl->chip_id == STM32_CHIPID_F411xx) { strcpy(map, memory_map_template_F4); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) { + } else if (sl->chip_id == STM32_CHIPID_F4_DE) { strcpy(map, memory_map_template_F4_DE); - } else if (sl->core_id == STM32F7_CORE_ID) { + } else if (sl->core_id == STM32_CORE_ID_M7F_SWD) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H74xxx) { + } else if (sl->chip_id == STM32_CHIPID_H74xxx) { snprintf(map, sz, memory_map_template_H7, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) { + } else if (sl->chip_id == STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F2) { + } else if (sl->chip_id == STM32_CHIPID_F2) { snprintf(map, sz, memory_map_template_F2, (unsigned int)sl->flash_size, (unsigned int)sl->sram_size, (unsigned int)sl->flash_size - 0x20000, (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); - } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x)) { + } else if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) { + } else if (sl->chip_id == STM32_CHIPID_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H72x) { + } else if (sl->chip_id == STM32_CHIPID_H72x) { snprintf(map, sz, memory_map_template_H72x3x, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); @@ -1847,7 +1847,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_close(sl); sl = stlink_open_usb(st->logging_level, st->connect_mode, st->serialnumber, st->freq); - if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) { cleanup(0); } + if (sl == NULL || sl->chip_id == STM32_CHIPID_UNKNOWN) { cleanup(0); } connected_stlink = sl; diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index f9de46f37..387d3ac68 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -429,7 +429,7 @@ static gchar *dev_format_chip_id(guint32 chip_id) { if (!params) { return(g_strdup_printf("0x%x", chip_id)); } - return(g_strdup(params->description)); + return(g_strdup(params->dev_type)); } static gchar *dev_format_mem_size(gsize flash_size) { diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 43a55a495..06e8571aa 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,3 +1,4 @@ +#include #include #include "chipid.h" @@ -7,905 +8,14 @@ #include #include -// This is the old chipid "database". -// It is kept here for now to be able to compare the -// result between the "old code" and the "new code". -// For now if you need to change something, please -// change it both here and in the corresponding -// config/chips/*.chip file. - -static struct stlink_chipid_params devices[] = { - { - // STM32F76x/F77x - // RM0410 - .chip_id = STLINK_CHIPID_STM32_F76xxx, - .description = "F76x/F77x", - .flash_type = STLINK_FLASH_TYPE_F7, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // "System memory" starting address from - .bootrom_size = 0xEDC0, - .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option - bytes, writing uses FLASH_F7_OPTCR - and FLASH_F7_OPTCR1 */ - .option_size = 0x20, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F74x/F75x - // RM0385, DS10916 - .chip_id = STLINK_CHIPID_STM32_F7, - .description = "F74x/F75x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F72x/F73x - // RM0431 - .chip_id = STLINK_CHIPID_STM32_F72xxx, - .description = "F72x/F73x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx medium-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_MD, - .description = "F1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx - // RM0033 (rev 5) - .chip_id = STLINK_CHIPID_STM32_F2, - .description = "F2xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_LD, - .description = "F1 Low-density device", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F4x5/F4x7 - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4, - .description = "F4x5/F4x7", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = STM32_F4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F46x/F47x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .description = "F46x/F47x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F42x/F43x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_HD, - .description = "F42x/F43x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_LP, - .description = "F401xB/C", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F411xx, - .description = "F411xC/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DE, - .description = "F401xD/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx high-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_HD, - .description = "F1xx High-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.1 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD, - .description = "L1xx Cat.1", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, // up to 16k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.2 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_CAT2, - .description = "L1xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.3 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, - .description = "L1xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.4 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, - .description = "L1xx Cat.4", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, // up to 48k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .option_base = STM32_L1_OPTION_BYTES_BASE, - .option_size = 8, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.5 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L152_RE, - .description = "L1xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, // up to 80k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx connectivity devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .description = "F1xx CL", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low- and medium-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, - .description = "F1xx Value Line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000, // 0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F446x family - // RM0390 - .chip_id = STLINK_CHIPID_STM32_F446, - .description = "F446", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F410 - // RM0401 - .chip_id = STLINK_CHIPID_STM32_F410, - .description = "F410", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x4000, - .sram_size = 0x8000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F303xB/C, STM32F358, STM32F302xBxC - // RM0316, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3, - .description = "F302/F303/F358", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx - // RM0313 - .chip_id = STLINK_CHIPID_STM32_F37x, - .description = "F37x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx high-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, - .description = "F1xx High-density value line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx XL-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_XLD, - .description = "F1xx XL-density", - .flash_type = STLINK_FLASH_TYPE_F1_XL, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F07x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .description = "F07x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F05x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0, - .description = "F05x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F412 - // RM0402 - .chip_id = STLINK_CHIPID_STM32_F412, - .description = "F412", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F413/F423 - // RM0430 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F413, - .description = "F413/F423", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector - // sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 - // only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F09x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F09x, - .description = "F09x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F04x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F04, - .description = "F04x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F03x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, - .description = "F03x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F301x6/8, STM32F302x6x8, STM32F318x8 - // RM0366, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3xx_SMALL, - .description = "F301/F302/F318", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L0xx Category 3 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0, - .description = "L0xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - }, - { - // STM32L0x Category 5 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .description = "L0xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x2000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32L0x Category 2 - // RM0367, RM0377 - .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .description = "L0xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - }, - { - // STM32F334, STM32F303x6/8, STM32F328 - // RM0364, RM0316 - .chip_id = STLINK_CHIPID_STM32_F334, - .description = "F303/F328/F334", // (RM0316 sec 33.6.1) - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0x3000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F303xD/E, STM32F398xE, STM32F302xD/E - // RM0316 (rev 5), RM0365 - .chip_id = STLINK_CHIPID_STM32_F303_HD, - .description = "F303 high density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L47x/L48x - // RM0351 - .chip_id = STLINK_CHIPID_STM32_L4, - .description = "L47x/L48x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4RX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4Rx, - .description = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4PX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4PX, - .description = "L4Px", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L41x_L42x - // RM0394 (rev 4), DS12469 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L41x_L42x, - .description = "L41x/L42x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, - // sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L43x_L44x - // RM0392 - .chip_id = STLINK_CHIPID_STM32_L43x_L44x, - .description = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L496x_L4A6x - // RM0351 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, - .description = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L45x_L46x - // RM0394 (updated version of RM0392?) - .chip_id = STLINK_CHIPID_STM32_L45x_L46x, - .description = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, - // page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system - // memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L0xx Category 1 - // RM0451, RM0377 - .chip_id = STLINK_CHIPID_STM32_L011, - .description = "L01x/L02x", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000, - }, - { - // STM32G030/031/041 - // RM0454, RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .description = "G03x/G04x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x2000, // 8k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G071/081 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .description = "G07x/G08x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G0B1/G0C1 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT3, - .description = "G0Bx/G0Cx", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32G051/G061 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT4, - .description = "G05x/G06x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G431/441 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT2, - .description = "G43x/G44x", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 16k at 0x20000000 - // SRAM2 is 6k at 0x20014000 - // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x8000, // 32k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G471/473/474/483/484 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT3, - .description = "G47x/G48x", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x20000, // 128k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G491/G4A1 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT4, - .description = "G49x/G4Ax", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x1C000, // 112k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE - // RM0434, RM0471 - .chip_id = STLINK_CHIPID_STM32_WB55, - .description = "WB5x/3x", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x1000, // 4k - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32WLEx - .chip_id = STLINK_CHIPID_STM32_WLE, - .description = "WLEx", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x800, // 2k - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H742/743/753 (from RM0433) - .chip_id = STLINK_CHIPID_STM32_H74xxx, - .description = "H74x/H75x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) - .flash_pagesize = 0x20000, // 128k sector (pg147) - .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H7A3/7B3 - // RM0455 - .chip_id = STLINK_CHIPID_STM32_H7Ax, - .description = "H7Ax/H7Bx", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) - .flash_pagesize = 0x2000, // 8k sector (p.146) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) - .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to - // two banks (Table 12-14) - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H72x/H73x - // RM0468 - .chip_id = STLINK_CHIPID_STM32_H72x, - .description = "H72x/H73x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) - .flash_pagesize = 0x20000, // 128k sector (p.152) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) - .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - - { - // unknown - .chip_id = STLINK_CHIPID_UNKNOWN, - .description = "unknown device", - .flash_type = STLINK_FLASH_TYPE_UNKNOWN, - .flash_size_reg = 0x0, - .flash_pagesize = 0x0, - .sram_size = 0x0, - .bootrom_base = 0x0, - .bootrom_size = 0x0, - }, -}; - -struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { - struct stlink_chipid_params *params = NULL; - - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) - if (devices[n].chip_id == chipid) { - params = &devices[n]; - break; - } - - return (params); -} - static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { - fprintf(fp, "# Chip-ID file for %s\n", dev->description); + fprintf(fp, "# Device Type: %s\n", dev->dev_type); + fprintf(fp, "# Reference Manual: RM%s\n", dev->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id 0x%x\n", dev->chip_id); - fprintf(fp, "description %s\n", dev->description); - fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_type %d\n", dev->flash_type); fprintf(fp, "flash_size_reg 0x%x\n", dev->flash_size_reg); fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); fprintf(fp, "sram_size 0x%x\n", dev->sram_size); @@ -916,46 +26,15 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "flags %d\n\n", dev->flags); } -static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) -{ - return p1->chip_id == p2->chip_id && - p1->description && p2->description && - strcmp(p1->description, p2->description) == 0 && - p1->flash_type == p2->flash_type && - p1->flash_size_reg == p2->flash_size_reg && - p1->flash_pagesize == p2->flash_pagesize && - p1->sram_size == p2->sram_size && - p1->bootrom_base == p2->bootrom_base && - p1->bootrom_size == p2->bootrom_size && - p1->option_base == p2->option_base && - p1->option_size == p2->option_size && - p1->flags == p2->flags; -} - -struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { +struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; - struct stlink_chipid_params *p2; - - //fprintf (stderr, "getparams: %x\n", chipid); for (params = devicelist; params != NULL; params = params->next) - if (params->chip_id == chipid) { + if (params->chip_id == chip_id) { + fprintf(stderr, "\ndetected chip_id parametres\n\n"); + dump_a_chip(stderr, params); break; } - p2 = stlink_chipid_get_params_old(chipid); - -#if 1 - if (params == NULL) { - params = p2; - } else if (!chipid_params_eq(params, p2)) { - // fprintf (stderr, "Error, chipid params not identical\n"); - // return NULL; - fprintf(stderr, "---------- old ------------\n"); - dump_a_chip(stderr, p2); - fprintf(stderr, "---------- new ------------\n"); - dump_a_chip(stderr, params); - } -#endif return(params); } @@ -966,7 +45,7 @@ void process_chipfile(char *fname) { struct stlink_chipid_params *ts; int nc; - // fprintf (stderr, "processing chipfile %s.\n", fname); + // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); if (!fp) { @@ -980,77 +59,103 @@ void process_chipfile(char *fname) { for (p = buf; isspace (*p); p++); if (!*p) { - continue; // we hit end-of-line wiht only whitespace + continue; // we hit end-of-line with only whitespace } if (*p == '#') { - continue; // ignore comments. + continue; // ignore comments } sscanf(p, "%s %s", word, value); - if (strcmp(word, "chip_id") == 0) { - if (sscanf(value, "%i", &ts->chip_id) < 1) { - fprintf(stderr, "Failed to parse chip id\n"); - } - } else if (strcmp (word, "description") == 0) { - // ts->description = strdup (value); + if (strcmp (word, "dev_type") == 0) { + // ts->dev_type = strdup (value); + buf[strlen(p) - 1] = 0; // chomp newline + sscanf(p, "%*s %n", &nc); + ts->dev_type = strdup(p + nc); + } else if (strcmp(word, "ref_manual_id") == 0) { + // ts->ref_manual_id = strdup (value); buf[strlen(p) - 1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); - ts->description = strdup(p + nc); - } else if (strcmp (word, "flash_type") == 0) { - if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { - fprintf(stderr, "Failed to parse flash type\n"); - } else if (ts->flash_type < STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) { - fprintf(stderr, "Unrecognized flash type\n"); + ts->ref_manual_id = strdup(p + nc); + } else if (strcmp(word, "chip_id") == 0) { + if (sscanf(value, "%i", &ts->chip_id) < 1) { + fprintf(stderr, "Failed to parse chip-id\n"); + } + } else if (strcmp(word, "flash_type") == 0) { + if (strcmp(value, "F0_F1_F3") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; + } else if (strcmp(value, "F1_XL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F1_XL; + } else if (strcmp(value, "F2_F4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F2_F4; + } else if (strcmp(value, "F7") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F7; + } else if (strcmp(value, "G0") == 0) { + ts->flash_type = STM32_FLASH_TYPE_G0; + } else if (strcmp(value, "G4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_G4; + } else if (strcmp(value, "H7") == 0) { + ts->flash_type = STM32_FLASH_TYPE_H7; + } else if (strcmp(value, "L0_L1") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L0_L1; + } else if (strcmp(value, "L4_L4P") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L4_L4P; + } else if (strcmp(value, "L5_U5") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L5_U5; + } else if (strcmp(value, "WB_WL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_WB_WL; + } else { + ts->flash_type = STM32_FLASH_TYPE_UNKNOWN; + fprintf(stderr, "Failed to parse flash type or unrecognized flash type\n"); } - } else if (strcmp (word, "flash_size_reg") == 0) { + } else if (strcmp(word, "flash_size_reg") == 0) { if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { fprintf(stderr, "Failed to parse flash size reg\n"); } - } else if (strcmp (word, "flash_pagesize") == 0) { + } else if (strcmp(word, "flash_pagesize") == 0) { if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { fprintf(stderr, "Failed to parse flash page size\n"); } - } else if (strcmp (word, "sram_size") == 0) { + } else if (strcmp(word, "sram_size") == 0) { if (sscanf(value, "%i", &ts->sram_size) < 1) { fprintf(stderr, "Failed to parse SRAM size\n"); } - } else if (strcmp (word, "bootrom_base") == 0) { + } else if (strcmp(word, "bootrom_base") == 0) { if (sscanf(value, "%i", &ts->bootrom_base) < 1) { fprintf(stderr, "Failed to parse BootROM base\n"); } - } else if (strcmp (word, "bootrom_size") == 0) { + } else if (strcmp(word, "bootrom_size") == 0) { if (sscanf(value, "%i", &ts->bootrom_size) < 1) { fprintf(stderr, "Failed to parse BootROM size\n"); } - } else if (strcmp (word, "option_base") == 0) { + } else if (strcmp(word, "option_base") == 0) { if (sscanf(value, "%i", &ts->option_base) < 1) { fprintf(stderr, "Failed to parse option base\n"); } - } else if (strcmp (word, "option_size") == 0) { + } else if (strcmp(word, "option_size") == 0) { if (sscanf(value, "%i", &ts->option_size) < 1) { fprintf(stderr, "Failed to parse option size\n"); } - } else if (strcmp (word, "flags") == 0) { + } else if (strcmp(word, "flags") == 0) { pp = strtok (p, " \t\n"); while ((pp = strtok (NULL, " \t\n"))) { - if (strcmp (pp, "none") == 0) { - ts->flags = 0; // not necessary: calloc did this already. - } else if (strcmp (pp, "dualbank") == 0) { + if (strcmp(pp, "none") == 0) { + // NOP + } else if (strcmp(pp, "dualbank") == 0) { ts->flags |= CHIP_F_HAS_DUAL_BANK; - } else if (strcmp (pp, "swo") == 0) { + } else if (strcmp(pp, "swo") == 0) { ts->flags |= CHIP_F_HAS_SWO_TRACING; } else { - fprintf (stderr, "Unknown flags word in %s: '%s'\n", + fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, pp); } } sscanf(value, "%x", &ts->flags); } else { - fprintf (stderr, "Unknown keyword in %s: %s\n", + fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); } } @@ -1059,37 +164,6 @@ void process_chipfile(char *fname) { devicelist = ts; } -void dump_chips (void) { - struct stlink_chipid_params *ts; - char *p, buf[100]; - FILE *fp; - - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { - ts = &devices[n]; - - strcpy(buf, ts->description); - - while ((p = strchr(buf, '/'))) // change slashes to underscore. - *p = '_'; - - strcat(buf, ".chip"); - fp = fopen(buf, "w"); - fprintf(fp, "# Chip-ID file for %s\n", ts->description); - fprintf(fp, "#\n"); - fprintf(fp, "chip_id %x\n", ts->chip_id); - fprintf(fp, "description %s\n", ts->description); - fprintf(fp, "flash_type %x\n", ts->flash_type); - fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); - fprintf(fp, "sram_size %x\n", ts->sram_size); - fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); - fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); - fprintf(fp, "option_base %x\n", ts->option_base); - fprintf(fp, "option_size %x\n", ts->option_size); - fprintf(fp, "flags %x\n\n", ts->flags); - fclose(fp); - } -} - #if defined(STLINK_HAVE_DIRENT_H) #include void init_chipids(char *dir_to_scan) { @@ -1102,7 +176,6 @@ void init_chipids(char *dir_to_scan) { } devicelist = NULL; - // dump_chips (); d = opendir(dir_to_scan); if (d) { @@ -1119,25 +192,8 @@ void init_chipids(char *dir_to_scan) { closedir(d); } else { perror (dir_to_scan); - return; // XXX - } - -#if 0 - { - struct stlink_chipid_params *p, *op; - int i; - p = devicelist; - - for (i = 0; i < 5; i++, p = p->next) { - op = stlink_chipid_get_params_old (p->chip_id); - fprintf (stderr, "---------- old ------------\n"); - dump_a_chip (stderr, op); - fprintf (stderr, "---------- new ------------\n"); - dump_a_chip (stderr, p); - - } + return; } -#endif } #endif //STLINK_HAVE_DIRENT_H @@ -1172,4 +228,5 @@ void init_chipids(char *dir_to_scan) { FindClose(hFind); } + #endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 20cfcf52d..458e7c3e2 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,87 +1,15 @@ #ifndef STLINK_CHIPID_H_ #define STLINK_CHIPID_H_ -#ifdef __cplusplus -extern "C" { -#endif +#include +#include -/** - * Chip IDs are explained in the appropriate programming manual for the - * DBGMCU_IDCODE register (0xE0042000) - * stm32 chipids, only lower 12 bits... - */ -enum stlink_stm32_chipids { - STLINK_CHIPID_UNKNOWN = 0x000, - - STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */ - STLINK_CHIPID_STM32_F2 = 0x411, - STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */ - STLINK_CHIPID_STM32_F4 = 0x413, - STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */ - STLINK_CHIPID_STM32_L4 = 0x415, - STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */ - STLINK_CHIPID_STM32_L0 = 0x417, - STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ - STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */ - STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ - STLINK_CHIPID_STM32_F446 = 0x421, - STLINK_CHIPID_STM32_F3 = 0x422, - STLINK_CHIPID_STM32_F4_LP = 0x423, - STLINK_CHIPID_STM32_L0_CAT2 = 0x425, - STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ - STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ - STLINK_CHIPID_STM32_L1_CAT2 = 0x429, - STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ - STLINK_CHIPID_STM32_F411xx = 0x431, - STLINK_CHIPID_STM32_F37x = 0x432, - STLINK_CHIPID_STM32_F4_DE = 0x433, - STLINK_CHIPID_STM32_F4_DSI = 0x434, - STLINK_CHIPID_STM32_L43x_L44x = 0x435, - STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ - STLINK_CHIPID_STM32_L152_RE = 0x437, - STLINK_CHIPID_STM32_F334 = 0x438, - STLINK_CHIPID_STM32_F3xx_SMALL = 0x439, - STLINK_CHIPID_STM32_F0 = 0x440, - STLINK_CHIPID_STM32_F412 = 0x441, - STLINK_CHIPID_STM32_F09x = 0x442, - STLINK_CHIPID_STM32_F0xx_SMALL = 0x444, - STLINK_CHIPID_STM32_F04 = 0x445, - STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ - STLINK_CHIPID_STM32_L0_CAT5 = 0x447, - STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the Nucleo F746ZG board */ - STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ - STLINK_CHIPID_STM32_F76xxx = 0x451, - STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the Nucleo F722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ - STLINK_CHIPID_STM32_L011 = 0x457, - STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ - STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, - STLINK_CHIPID_STM32_L45x_L46x = 0x462, - STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_L41x_L42x = 0x464, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ - STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, s46.6.1 "MCU device ID code" */ - STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p. 2247, found on the STM32L4R9I-DISCO board */ - STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p. 2247 */ - STLINK_CHIPID_STM32_G4_CAT4 = 0x479, - STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ - STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ - STLINK_CHIPID_STM32_WB55 = 0x495, - STLINK_CHIPID_STM32_WLE = 0x497 -}; - -#define CHIP_F_HAS_DUAL_BANK (1 << 0) -#define CHIP_F_HAS_SWO_TRACING (1 << 1) - -/** Chipid parameters */ +/** Chipid parametres */ struct stlink_chipid_params { + char *dev_type; + char *ref_manual_id; uint32_t chip_id; - char *description; - enum stlink_flash_type flash_type; + enum stm32_flash_type flash_type; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; @@ -93,12 +21,7 @@ struct stlink_chipid_params { struct stlink_chipid_params * next; }; - struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); -#ifdef __cplusplus -} -#endif - #endif // STLINK_CHIPID_H_ diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 7076a2cfa..94978a51f 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -2,21 +2,21 @@ #include #include +#include #include #include #include "flash_loader.h" -#define FLASH_REGS_BANK2_OFS 0x40 -#define FLASH_BANK2_START_ADDR 0x08080000 +#define FLASH_REGS_BANK2_OFS 0x40 +#define FLASH_BANK2_START_ADDR 0x08080000 #define STM32F0_WDG_KR 0x40003000 #define STM32H7_WDG_KR 0x58004800 #define STM32F0_WDG_KR_KEY_RELOAD 0xAAAA -/* !!! - * !!! DO NOT MODIFY FLASH LOADERS DIRECTLY! - * !!! +/* + * !!! DO NOT MODIFY FLASH LOADERS DIRECTLY !!! * * Edit assembly files in the '/flashloaders' instead. The sizes of binary * flash loaders must be aligned by 4 (it's written by stlink_write_mem32) @@ -154,8 +154,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; uint32_t dfsr, cfsr, hfsr; - /* Interrupt masking. - * According to DDI0419C, Table C1-7 firstly force halt */ + /* Interrupt masking according to DDI0419C, Table C1-7 firstly force halt */ stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | STLINK_REG_DHCSR_C_HALT); @@ -176,7 +175,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { ILOG("Successfully loaded flash loader in sram\n"); // set address of IWDG key register for reset it - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { fl->iwdg_kr = STM32H7_WDG_KR; } else { fl->iwdg_kr = STM32F0_WDG_KR; @@ -233,43 +232,43 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STLINK_CHIPID_STM32_L1_MD || - sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS_HD || - sl->chip_id == STLINK_CHIPID_STM32_L152_RE || - sl->chip_id == STLINK_CHIPID_STM32_L011 || - sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { + if (sl->chip_id == STM32_CHIPID_L1_MD || + sl->chip_id == STM32_CHIPID_L1_CAT2 || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS_HD || + sl->chip_id == STM32_CHIPID_L152_RE || + sl->chip_id == STM32_CHIPID_L011 || + sl->chip_id == STM32_CHIPID_L0 || + sl->chip_id == STM32_CHIPID_L0_CAT5 || + sl->chip_id == STM32_CHIPID_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); - } else if (sl->core_id == STM32VL_CORE_ID || - sl->chip_id == STLINK_CHIPID_STM32_F1_MD || - sl->chip_id == STLINK_CHIPID_STM32_F1_HD || - sl->chip_id == STLINK_CHIPID_STM32_F1_LD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_HD || - sl->chip_id == STLINK_CHIPID_STM32_F1_XLD || - sl->chip_id == STLINK_CHIPID_STM32_F1_CONN || - sl->chip_id == STLINK_CHIPID_STM32_F3 || - sl->chip_id == STLINK_CHIPID_STM32_F3xx_SMALL || - sl->chip_id == STLINK_CHIPID_STM32_F303_HD || - sl->chip_id == STLINK_CHIPID_STM32_F37x || - sl->chip_id == STLINK_CHIPID_STM32_F334) { + } else if (sl->core_id == STM32_CORE_ID_M3_r1p1_SWD || + sl->chip_id == STM32_CHIPID_F1_MD || + sl->chip_id == STM32_CHIPID_F1_HD || + sl->chip_id == STM32_CHIPID_F1_LD || + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_F1_VL_HD || + sl->chip_id == STM32_CHIPID_F1_XLD || + sl->chip_id == STM32_CHIPID_F1_CONN || + sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F3xx_SMALL || + sl->chip_id == STM32_CHIPID_F303_HD || + sl->chip_id == STM32_CHIPID_F37x || + sl->chip_id == STM32_CHIPID_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411xx || - sl->chip_id == STLINK_CHIPID_STM32_F412 || - sl->chip_id == STLINK_CHIPID_STM32_F413 || - sl->chip_id == STLINK_CHIPID_STM32_F446) { + } else if (sl->chip_id == STM32_CHIPID_F2 || + sl->chip_id == STM32_CHIPID_F4 || + sl->chip_id == STM32_CHIPID_F4_DE || + sl->chip_id == STM32_CHIPID_F4_LP || + sl->chip_id == STM32_CHIPID_F4_HD || + sl->chip_id == STM32_CHIPID_F4_DSI || + sl->chip_id == STM32_CHIPID_F410 || + sl->chip_id == STM32_CHIPID_F411xx || + sl->chip_id == STM32_CHIPID_F412 || + sl->chip_id == STM32_CHIPID_F413 || + sl->chip_id == STM32_CHIPID_F446) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -277,10 +276,10 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); if (retval == -1) { return(retval); } - } else if (sl->core_id == STM32F7_CORE_ID || - sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx || - sl->chip_id == STLINK_CHIPID_STM32_F72xxx) { + } else if (sl->core_id == STM32_CORE_ID_M7F_SWD || + sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx || + sl->chip_id == STM32_CHIPID_F72xxx) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -288,19 +287,19 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); if (retval == -1) { return(retval); } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || - sl->chip_id == STLINK_CHIPID_STM32_F04 || - sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || - sl->chip_id == STLINK_CHIPID_STM32_F0xx_SMALL || - sl->chip_id == STLINK_CHIPID_STM32_F09x) { + } else if (sl->chip_id == STM32_CHIPID_F0 || + sl->chip_id == STM32_CHIPID_F04 || + sl->chip_id == STM32_CHIPID_F0_CAN || + sl->chip_id == STM32_CHIPID_F0xx_SMALL || + sl->chip_id == STM32_CHIPID_F09x) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); - } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L41x_L42x) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STLINK_CHIPID_STM32_L4Rx) || - (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x)) { + } else if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L41x_L42x) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_L4Rx) || + (sl->chip_id == STM32_CHIPID_L496x_L4A6x)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { @@ -333,7 +332,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return(-1); } - if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } @@ -353,7 +352,8 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe /* Run loader */ stlink_run(sl, RUN_FLASH_LOADER); -/* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. +/* + * This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when * "something goes wrong" that requires the error message "flash loader run error" would wait @@ -382,7 +382,8 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // check written byte count stlink_read_reg(sl, 2, &rr); - /* The chunk size for loading is not rounded. The flash loader + /* + * The chunk size for loading is not rounded. The flash loader * subtracts the size of the written block (1-8 bytes) from * the remaining size each time. A negative value may mean that * several bytes garbage has been written due to the unaligned diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 29fd5b068..85b92bef3 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -4,6 +4,7 @@ * This should contain all the common top level stlink interfaces, * regardless of how the backend does the work.... */ + #ifndef STLINK_FLASH_LOADER_H_ #define STLINK_FLASH_LOADER_H_ @@ -12,16 +13,8 @@ #include -#ifdef __cplusplus -extern "C" { -#endif - int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); -#ifdef __cplusplus -} -#endif - #endif // STLINK_FLASH_LOADER_H_ diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index a2dfc6d26..c7562e290 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -4,21 +4,20 @@ #include /* - - libusb ver | LIBUSB_API_VERSION - -----------+-------------------- - v1.0.13 | 0x01000100 - v1.0.14 | 0x010000FF - v1.0.15 | 0x01000101 - v1.0.16 | 0x01000102 - v1.0.17 | 0x01000102 - v1.0.18 | 0x01000102 - v1.0.19 | 0x01000103 - v1.0.20 | 0x01000104 - v1.0.21 | 0x01000105 - v1.0.22 | 0x01000106 - v1.0.23 | 0x01000107 - + * libusb ver | LIBUSB_API_VERSION + * -----------+-------------------- + * v1.0.13 | 0x01000100 + * v1.0.14 | 0x010000FF + * v1.0.15 | 0x01000101 + * v1.0.16 | 0x01000102 + * v1.0.17 | 0x01000102 + * v1.0.18 | 0x01000102 + * v1.0.19 | 0x01000103 + * v1.0.20 | 0x01000104 + * v1.0.21 | 0x01000105 + * v1.0.22 | 0x01000106 + * v1.0.23 | 0x01000107 + * v1.0.24 | 0x01000108 */ #if defined (__FreeBSD__) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 817f3d68e..79924fc20 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -4,6 +4,7 @@ * Slow, yet another wheel reinvented, but enough to make the rest of our code * pretty enough. */ + #include #include #include diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 18792c89f..feab40c13 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -74,7 +74,6 @@ * part to an existing options line for usb-storage). */ - #define __USE_GNU #include #include diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index f34b2e122..212d03b27 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -9,10 +9,6 @@ #include #include -#ifdef __cplusplus -extern "C" { -#endif - /* Device access */ #define RDWR 0 #define RO 1 @@ -60,8 +56,4 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); -#ifdef __cplusplus -} -#endif - #endif // STLINK_SG_H diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index c6b71ba4e..3f4b71e51 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -12,10 +12,6 @@ #include #include "logging.h" -#ifdef __cplusplus -extern "C" { -#endif - #define STLINK_USB_VID_ST 0x0483 #define STLINK_USB_PID_STLINK 0x3744 #define STLINK_USB_PID_STLINK_32L 0x3748 @@ -69,12 +65,9 @@ struct stlink_libusb { * @retval NULL Error while opening the stlink * @retval !NULL Stlink found and ready to use */ + stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); -#ifdef __cplusplus -} -#endif - #endif // STLINK_USB_H diff --git a/src/win32/mmap.h b/src/win32/mmap.h index 1f2e756cb..06079a9bc 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -13,17 +13,9 @@ #define MAP_ANONYMOUS (1 << 5) #define MAP_FAILED ((void *)-1) -#ifdef __cplusplus -extern "C" { -#endif - void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); int munmap(void *addr, size_t len); -#ifdef __cplusplus -} -#endif - #endif /* HAVE_SYS_MMAN_H */ #endif /* STLINK_MMAP_H */ diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c index 08da60b85..422731b3f 100644 --- a/src/win32/sys_time.c +++ b/src/win32/sys_time.c @@ -30,4 +30,5 @@ int gettimeofday(struct timeval *tv, struct timezone *tz) { return 0; } + #endif //STLINK_HAVE_SYS_TIME_H diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index 39f97f739..d314509b7 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -12,16 +12,8 @@ struct timezone { int tz_dsttime; }; -#ifdef __cplusplus -extern "C" { -#endif - int gettimeofday(struct timeval *tv, struct timezone *tz); -#ifdef __cplusplus -} -#endif - #endif /* STLINK_HAVE_SYS_TIME_H */ #endif /* STLINK_TIME_H */ diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index bfdcac5ce..3f4d28bbd 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -123,7 +123,8 @@ static void set_socket_errno(int winsock_err) { } } -/* A wrapper around the socket() function. +/* + * A wrapper around the socket() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ @@ -135,7 +136,8 @@ SOCKET win32_socket(int domain, int type, int protocol) { return(fd); } -/* A wrapper around the connect() function. +/* + * A wrapper around the connect() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index 5f8f09589..614046a6f 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -20,7 +20,8 @@ #pragma warning(pop) #endif -/* winsock doesn't feature poll(), so there is a version implemented in terms of select() in win32_socket.c. +/* + * winsock doesn't feature poll(), so there is a version implemented in terms of select() in win32_socket.c. * The following definitions are copied from linux man pages. * A poll() macro is defined to call the version in win32_socket.c. */ @@ -40,7 +41,8 @@ struct pollfd { #endif #define poll(x, y, z) win32_poll(x, y, z) -/* These wrappers do nothing special except set the global errno variable if an error occurs +/* + * These wrappers do nothing special except set the global errno variable if an error occurs * (winsock doesn't do this by default). * They set errno to unix-like values (i.e. WSAEWOULDBLOCK is mapped to EAGAIN), * so code outside of this file "shouldn't" have to worry about winsock specific error handling.