From c8456dce06beeb1d3baf0862dac233fe97b56613 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Sun, 15 May 2022 07:03:46 +0900 Subject: [PATCH] dcache: Fix issue with missing writes during invalidate This again fixes: #122 Testing to see how it helps with: #146 However, this time I hope it is more stable as formal now caught this bug and now asserts that the formal properties pass. The fix is slightly different than the original as now we only change the state machine to allow going directly from INVALIDATE to WRITE with write having higher priority over invalidate as per comment. --- rtl/verilog/mor1kx_dcache.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/rtl/verilog/mor1kx_dcache.v b/rtl/verilog/mor1kx_dcache.v index 5943dc0b..692d2236 100644 --- a/rtl/verilog/mor1kx_dcache.v +++ b/rtl/verilog/mor1kx_dcache.v @@ -513,7 +513,13 @@ module mor1kx_dcache end INVALIDATE: begin - if (invalidate) begin + if (cpu_we_i) begin + // If we get a write while we are in invalidate its because + // We have already acked the invalidate and the control unit + // has moved on. So start the write as if we were in READ + // or idle. + state <= WRITE; + end else if (invalidate) begin // Store address in invalidate_adr that is muxed to the tag // memory write address invalidate_adr <= spr_bus_dat_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];