From 590e368f38469ace2f97103e712263e158ebf358 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Thu, 3 Jan 2019 06:24:45 +0900 Subject: [PATCH] Fix resource issue with non inferring RAM (#66) Itroduced with commit 73bf629 (true_dpram: Use a single sequential block). Revert it back to fix the resource issue. --- rtl/verilog/mor1kx_true_dpram_sclk.v | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/rtl/verilog/mor1kx_true_dpram_sclk.v b/rtl/verilog/mor1kx_true_dpram_sclk.v index 2b186568..deefa277 100644 --- a/rtl/verilog/mor1kx_true_dpram_sclk.v +++ b/rtl/verilog/mor1kx_true_dpram_sclk.v @@ -42,7 +42,11 @@ module mor1kx_true_dpram_sclk end else begin rdata_a <= mem[addr_a]; end + end + /* Keep these two blocks separate even if Synopsys DC and Spyglass lint + complain. Combining them causes quartus to fail to infer RAM blocks. */ + always @(posedge clk) begin if (we_b) begin mem[addr_b] <= din_b; rdata_b <= din_b;