zero-riscy CPU Core

Hardware implementation of the SHA-256 cryptographic hash function

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A small, light weight, RISC CPU soft core

A bit-serial CPU written in VHDL, with a simulator written in C.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

A Forth CPU and System on a Chip, based on the J1, written in VHDL

16 bit serial multiplier in SystemVerilog

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

5-stage pipelined 32-bit MIPS microprocessor in Verilog

The OpenPiton Platform

OpenTitan: Open source silicon root of trust