From bd742a9086b0d5d7b6bb03d50d3c298086f01939 Mon Sep 17 00:00:00 2001 From: Luca Versari Date: Sun, 10 Nov 2024 11:36:50 +0100 Subject: [PATCH] ABI checks: add support for tier2 arches See #131800 for the data collection behind this change. --- compiler/rustc_target/src/target_features.rs | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/compiler/rustc_target/src/target_features.rs b/compiler/rustc_target/src/target_features.rs index c4f9c742650d7..32575a1bed664 100644 --- a/compiler/rustc_target/src/target_features.rs +++ b/compiler/rustc_target/src/target_features.rs @@ -582,6 +582,13 @@ pub fn all_rust_features() -> impl Iterator { const X86_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "sse"), (256, "avx"), (512, "avx512f")]; const AARCH64_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "neon")]; +const ARM_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "neon")]; +const POWERPC_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "altivec")]; +const RISCV_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = + &[(32, "zve32x"), (64, "zve64x"), (128, "zvl128b")]; +const WASM_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "simd128")]; +const S390X_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "vector")]; +const SPARC_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(64, "v9")]; impl super::spec::Target { pub fn rust_target_features(&self) -> &'static [(&'static str, Stability, ImpliedFeatures)] { @@ -606,9 +613,18 @@ impl super::spec::Target { // Returns None if we do not support ABI checks on the given target yet. pub fn features_for_correct_vector_abi(&self) -> Option<&'static [(u64, &'static str)]> { match &*self.arch { + // Tier 1 "x86" | "x86_64" => Some(X86_FEATURES_FOR_CORRECT_VECTOR_ABI), "aarch64" => Some(AARCH64_FEATURES_FOR_CORRECT_VECTOR_ABI), - // FIXME: add support for non-tier1 architectures + // Tier 2 + "arm" => Some(ARM_FEATURES_FOR_CORRECT_VECTOR_ABI), + "powerpc" | "powerpc64" => Some(POWERPC_FEATURES_FOR_CORRECT_VECTOR_ABI), + "loongarch" => Some(&[]), // on-stack ABI, so we complain about all by-val vectors + "riscv32" | "riscv64" => Some(RISCV_FEATURES_FOR_CORRECT_VECTOR_ABI), + "wasm32" | "wasm64" => Some(WASM_FEATURES_FOR_CORRECT_VECTOR_ABI), + "s390x" => Some(S390X_FEATURES_FOR_CORRECT_VECTOR_ABI), + "sparc" | "sparc64" => Some(SPARC_FEATURES_FOR_CORRECT_VECTOR_ABI), + // FIXME: add support for non-tier2 architectures _ => None, } }