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Wrong senvcfg check for systems without S-mode support #1898

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mimiqdev opened this issue Jan 21, 2025 · 2 comments · May be fixed by #1899
Open

Wrong senvcfg check for systems without S-mode support #1898

mimiqdev opened this issue Jan 21, 2025 · 2 comments · May be fixed by #1899

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@mimiqdev
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In Spike's require_envcfg macro, it checks senvcfg even when S-mode is not supported:

#define require_envcfg(field) \
  do { \
    if (((STATE.prv != PRV_M) && (m##field == 0)) || \
        ((STATE.prv == PRV_U && !STATE.v) && (s##field == 0))) \
      throw trap_illegal_instruction(insn.bits()); \
    else if (STATE.v && ((h##field == 0) || \
                        ((STATE.prv == PRV_U) && (s##field == 0)))) \
      throw trap_virtual_instruction(insn.bits()); \
  } while (0);

This is problematic for systems that don't implement S-mode. The current implementation would incorrectly check s##field (like senvcfg.CBIE for CBO.FLUSH instruction) even when S-mode is not supported.
The discussion in the CMO spec repo riscv/riscv-CMOs#71

Possible fixes:

#define require_envcfg(field) \
  do { \
    if ((STATE.prv != PRV_M) && (m##field == 0)) \
      throw trap_illegal_instruction(insn.bits()); \
    if (p->extension_enabled_const('S') && (STATE.prv == PRV_U && !STATE.v) && (s##field == 0)) \
      throw trap_illegal_instruction(insn.bits()); \
    else if (STATE.v && ((h##field == 0) || \
                        (p->extension_enabled_const('S') && (STATE.prv == PRV_U) && (s##field == 0)))) \
      throw trap_virtual_instruction(insn.bits()); \
  } while (0);
@aswaterman
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Your proposed fix looks correct to me. Would you mind issuing a pull request?

@mimiqdev
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Thanks for the reply, I'll create a PR.

@mimiqdev mimiqdev linked a pull request Jan 21, 2025 that will close this issue
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Fix envcfg check when S-mode is not available mimiqdev/riscv-isa-sim
2 participants
@aswaterman @mimiqdev