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nrf51.svd
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<?xml version="1.0" encoding="utf-8"?>
<!-- File naming: <vendor>_<part/series name>_svd.xml -->
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
<vendor>Nordic Semiconductor</vendor> <!-- Name for Doxygroup -->
<vendorID>Nordic</vendorID> <!-- Vendor ID -->
<name>nrf51</name> <!-- Official name of part or part series -->
<series>nrf51</series>
<version>522</version> <!-- Version of this description. It is the run of the automatic generation of SUS. -->
<description>nRF51 reference description for radio MCU with ARM 32-bit Cortex-M0 Microcontroller at 16MHz CPU clock</description>
<licenseText>
Copyright (c) 2013, Nordic Semiconductor ASA\n
All rights reserved.\n
\n
Redistribution and use in source and binary forms, with or without\n
modification, are permitted provided that the following conditions are met:\n
\n
* Redistributions of source code must retain the above copyright notice, this\n
list of conditions and the following disclaimer.\n
\n
* Redistributions in binary form must reproduce the above copyright notice,\n
this list of conditions and the following disclaimer in the documentation\n
and/or other materials provided with the distribution.\n
\n
* Neither the name of Nordic Semiconductor ASA nor the names of its\n
contributors may be used to endorse or promote products derived from\n
this software without specific prior written permission.\n
\n
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n
</licenseText>
<!-- Register Properties Group -->
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
and register that do not define "size" themselves -->
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
<cpu>
<name>CM0</name>
<revision>r3p1</revision> <!-- CPU Revision r3p1 = 0x2000 -->
<endian>little</endian> <!-- little, big, configurable (headerfile: little, big, configurable (#ifdef compilerflag) -->
<mpuPresent>0</mpuPresent> <!-- Does the CPU has a MPU? {0|1} -->
<fpuPresent>0</fpuPresent> <!-- Does the CPU has a FPU? {0|1} -->
<nvicPrioBits>2</nvicPrioBits> <!-- Number of NVIC Priority Bits {8..2} -->
<vendorSystickConfig>0</vendorSystickConfig> <!-- Does the Vendor has his own Systick Configuration Function? See CMSIS: core_cm3.h -->
</cpu>
<headerSystemFilename>system_nrf51</headerSystemFilename> <!-- System Header File overwrite -->
<headerDefinitionsPrefix>NRF_</headerDefinitionsPrefix> <!-- Prefix for all structs and #defines -->
<vendorExtensions>
<ExampleStackSize>2048</ExampleStackSize> <!-- Default stack size used in Nordic's startup_nrf51.s files. [Byte/decimal] -->
<ExampleHeapSize>2048</ExampleHeapSize> <!-- Default heap size used in Nordic's startup_nrf51.s files. [Byte/decimal] -->
<MaxInterrupts>32</MaxInterrupts> <!-- Number of interrupts used in Nordic's startup_nrf51.s files. [Byte/decimal] -->
</vendorExtensions>
<peripherals>
<peripheral>
<name>POWER</name>
<version>522</version>
<description>Power Control.</description>
<groupName>POWER</groupName>
<baseAddress>0x40000000</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>POWER_CLOCK</name>
<value>0</value>
</interrupt>
<registers>
<register>
<name>TASKS_CONSTLAT</name>
<description>Enable constant latency mode.</description>
<addressOffset>0x078</addressOffset>
<access>write-only</access>
</register>
<register>
<name>TASKS_LOWPWR</name>
<description>Enable low power mode (variable latency).</description>
<addressOffset>0x07C</addressOffset>
<access>write-only</access>
</register>
<register>
<name>EVENTS_POFWARN</name>
<description>Power failure warning.</description>
<addressOffset>0x108</addressOffset>
</register>
<register>
<name>INTENSET</name>
<description>Interrupt enable set register.</description>
<addressOffset>0x304</addressOffset>
<fields>
<field>
<name>POFWARN</name>
<description>Enable interrupt on POFWARN event.</description>
<lsb>2</lsb> <msb>2</msb>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>Disabled</name>
<description>Interrupt disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Interrupt enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
<description>Enable interrupt on write.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INTENCLR</name>
<description>Interrupt enable clear register.</description>
<addressOffset>0x308</addressOffset>
<fields>
<field>
<name>POFWARN</name>
<description>Disable interrupt on POFWARN event.</description>
<lsb>2</lsb> <msb>2</msb>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>Disabled</name>
<description>Interrupt disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Interrupt enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
<description>Disable interrupt on write.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RESETREAS</name>
<description>Reset reason.</description>
<addressOffset>0x400</addressOffset>
<fields>
<field>
<name>RESETPIN</name>
<description>Reset from pin-reset detected.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
<name>NotDetected</name>
<description>Reset not detected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Detected</name>
<description>Reset detected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DOG</name>
<description>Reset from watchdog detected.</description>
<lsb>1</lsb> <msb>1</msb>
<enumeratedValues>
<enumeratedValue>
<name>NotDetected</name>
<description>Reset not detected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Detected</name>
<description>Reset detected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SREQ</name>
<description>Reset from AIRCR.SYSRESETREQ detected.</description>
<lsb>2</lsb> <msb>2</msb>
<enumeratedValues>
<enumeratedValue>
<name>NotDetected</name>
<description>Reset not detected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Detected</name>
<description>Reset detected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCKUP</name>
<description>Reset from CPU lock-up detected.</description>
<lsb>3</lsb> <msb>3</msb>
<enumeratedValues>
<enumeratedValue>
<name>NotDetected</name>
<description>Reset not detected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Detected</name>
<description>Reset detected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OFF</name>
<description>Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO.</description>
<lsb>16</lsb> <msb>16</msb>
<enumeratedValues>
<enumeratedValue>
<name>NotDetected</name>
<description>Reset not detected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Detected</name>
<description>Reset detected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPCOMP</name>
<description>Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP.</description>
<lsb>17</lsb> <msb>17</msb>
<enumeratedValues>
<enumeratedValue>
<name>NotDetected</name>
<description>Reset not detected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Detected</name>
<description>Reset detected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIF</name>
<description>Reset from wake-up from OFF mode detected by entering into debug interface mode.</description>
<lsb>18</lsb> <msb>18</msb>
<enumeratedValues>
<enumeratedValue>
<name>NotDetected</name>
<description>Reset not detected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Detected</name>
<description>Reset detected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RAMSTATUS</name>
<description>Ram status register.</description>
<addressOffset>0x428</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>RAMBLOCK0</name>
<description>RAM block 0 status.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
<name>Off</name>
<description>RAM block 0 is off or powering up.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>On</name>
<description>RAM block 0 is on.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAMBLOCK1</name>
<description>RAM block 1 status.</description>
<lsb>1</lsb> <msb>1</msb>
<enumeratedValues>
<enumeratedValue>
<name>Off</name>
<description>RAM block 1 is off or powering up.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>On</name>
<description>RAM block 1 is on.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAMBLOCK2</name>
<description>RAM block 2 status.</description>
<lsb>2</lsb> <msb>2</msb>
<enumeratedValues>
<enumeratedValue>
<name>Off</name>
<description>RAM block 2 is off or powering up.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>On</name>
<description>RAM block 2 is on.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAMBLOCK3</name>
<description>RAM block 3 status.</description>
<lsb>3</lsb> <msb>3</msb>
<enumeratedValues>
<enumeratedValue>
<name>Off</name>
<description>RAM block 3 is off or powering up.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>On</name>
<description>RAM block 3 is on.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYSTEMOFF</name>
<description>System off register.</description>
<addressOffset>0x500</addressOffset>
<access>write-only</access>
<fields>
<field>
<name>SYSTEMOFF</name>
<description>Enter system off mode.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
<name>Enter</name>
<description>Enter system off mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>POFCON</name>
<description>Power failure configuration.</description>
<addressOffset>0x510</addressOffset>
<fields>
<field>
<name>POF</name>
<description>Power failure comparator enable.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
<name>Disabled</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>THRESHOLD</name>
<description>Set threshold level.</description>
<lsb>1</lsb> <msb>2</msb>
<enumeratedValues>
<enumeratedValue>
<name>V21</name>
<description>Set threshold to 2.1Volts.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>V23</name>
<description>Set threshold to 2.3Volts.</description>
<value>0x01</value>
</enumeratedValue>
<enumeratedValue>
<name>V25</name>
<description>Set threshold to 2.5Volts.</description>
<value>0x02</value>
</enumeratedValue>
<enumeratedValue>
<name>V27</name>
<description>Set threshold to 2.7Volts.</description>
<value>0x03</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPREGRET</name>
<description>General purpose retention register. This register is a retained register.</description>
<addressOffset>0x51C</addressOffset>
<fields>
<field>
<name>GPREGRET</name>
<description>General purpose retention register.</description>
<lsb>0</lsb> <msb>7</msb>
</field>
</fields>
</register>
<register>
<name>RAMON</name>
<description>Ram on/off.</description>
<addressOffset>0x524</addressOffset>
<resetValue>0x00000003</resetValue>
<fields>
<field>
<name>ONRAM0</name>
<description>RAM block 0 behaviour in ON mode.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
<name>RAM0Off</name>
<description>RAM block 0 OFF in ON mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RAM0On</name>
<description>RAM block 0 ON in ON mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONRAM1</name>
<description>RAM block 1 behaviour in ON mode.</description>
<lsb>1</lsb> <msb>1</msb>
<enumeratedValues>
<enumeratedValue>
<name>RAM1Off</name>
<description>RAM block 1 OFF in ON mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RAM1On</name>
<description>RAM block 1 ON in ON mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OFFRAM0</name>
<description>RAM block 0 behaviour in OFF mode.</description>
<lsb>16</lsb> <msb>16</msb>
<enumeratedValues>
<enumeratedValue>
<name>RAM0Off</name>
<description>RAM block 0 OFF in OFF mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RAM0On</name>
<description>RAM block 0 ON in OFF mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OFFRAM1</name>
<description>RAM block 1 behaviour in OFF mode.</description>
<lsb>17</lsb> <msb>17</msb>
<enumeratedValues>
<enumeratedValue>
<name>RAM1Off</name>
<description>RAM block 1 OFF in OFF mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RAM1On</name>
<description>RAM block 1 ON in OFF mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RESET</name>
<description>Pin reset functionality configuration register. This register is a retained register.</description>
<addressOffset>0x544</addressOffset>
<fields>
<field>
<name>RESET</name>
<description>Enable or disable pin reset in debug interface mode.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
<name>Disabled</name>
<description>Pin reset in debug interface mode disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Pin reset in debug interface mode enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RAMONB</name>
<description>Ram on/off.</description>
<addressOffset>0x554</addressOffset>
<resetValue>0x00000003</resetValue>
<fields>
<field>
<name>ONRAM2</name>
<description>RAM block 2 behaviour in ON mode.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
<name>RAM2Off</name>
<description>RAM block 2 OFF in ON mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RAM2On</name>
<description>RAM block 2 ON in ON mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONRAM3</name>
<description>RAM block 3 behaviour in ON mode.</description>
<lsb>1</lsb> <msb>1</msb>
<enumeratedValues>
<enumeratedValue>
<name>RAM3Off</name>
<description>RAM block 33 OFF in ON mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RAM3On</name>
<description>RAM block 3 ON in ON mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OFFRAM2</name>
<description>RAM block 2 behaviour in OFF mode.</description>
<lsb>16</lsb> <msb>16</msb>
<enumeratedValues>
<enumeratedValue>
<name>RAM2Off</name>
<description>RAM block 2 OFF in OFF mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RAM2On</name>
<description>RAM block 2 ON in OFF mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OFFRAM3</name>
<description>RAM block 3 behaviour in OFF mode.</description>
<lsb>17</lsb> <msb>17</msb>
<enumeratedValues>
<enumeratedValue>
<name>RAM3Off</name>
<description>RAM block 3 OFF in OFF mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RAM3On</name>
<description>RAM block 3 ON in OFF mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DCDCEN</name>
<description>DCDC converter enable configuration register.</description>
<addressOffset>0x578</addressOffset>
<fields>
<field>
<name>DCDCEN</name>
<description>Enable DCDC converter.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
<name>Disabled</name>
<description>DCDC converter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>DCDC converter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DCDCFORCE</name>
<description>DCDC power-up force register.</description>
<addressOffset>0xA08</addressOffset>
<fields>
<field>
<name>FORCEOFF</name>
<description>DCDC power-up force off.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
<name>NoForce</name>
<description>No force.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Force</name>
<description>Force.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FORCEON</name>
<description>DCDC power-up force on.</description>
<lsb>1</lsb> <msb>1</msb>
<enumeratedValues>
<enumeratedValue>
<name>NoForce</name>
<description>No force.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Force</name>
<description>Force.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CLOCK</name>
<version>522</version>
<description>Clock control.</description>
<groupName>CLOCK</groupName>
<baseAddress>0x40000000</baseAddress>
<size>32</size>
<access>read-write</access>
<alternatePeripheral>POWER</alternatePeripheral>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>POWER_CLOCK</name>
<value>0</value>
</interrupt>
<registers>
<register>
<name>TASKS_HFCLKSTART</name>
<description>Start HFCLK clock source.</description>
<addressOffset>0x000</addressOffset>
<access>write-only</access>
</register>
<register>
<name>TASKS_HFCLKSTOP</name>
<description>Stop HFCLK clock source.</description>
<addressOffset>0x004</addressOffset>
<access>write-only</access>
</register>
<register>
<name>TASKS_LFCLKSTART</name>
<description>Start LFCLK clock source.</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
</register>
<register>
<name>TASKS_LFCLKSTOP</name>
<description>Stop LFCLK clock source.</description>
<addressOffset>0x00C</addressOffset>
<access>write-only</access>
</register>
<register>
<name>TASKS_CAL</name>
<description>Start calibration of LFCLK RC oscillator.</description>
<addressOffset>0x010</addressOffset>
<access>write-only</access>
</register>
<register>
<name>TASKS_CTSTART</name>
<description>Start calibration timer.</description>
<addressOffset>0x014</addressOffset>
<access>write-only</access>
</register>
<register>
<name>TASKS_CTSTOP</name>
<description>Stop calibration timer.</description>
<addressOffset>0x018</addressOffset>
<access>write-only</access>
</register>
<register>
<name>EVENTS_HFCLKSTARTED</name>
<description>HFCLK oscillator started.</description>
<addressOffset>0x100</addressOffset>
</register>
<register>
<name>EVENTS_LFCLKSTARTED</name>
<description>LFCLK oscillator started.</description>
<addressOffset>0x104</addressOffset>
</register>
<register>
<name>EVENTS_DONE</name>
<description>Calibration of LFCLK RC oscillator completed.</description>
<addressOffset>0x10C</addressOffset>
</register>
<register>
<name>EVENTS_CTTO</name>
<description>Calibration timer timeout.</description>
<addressOffset>0x110</addressOffset>
</register>
<register>
<name>INTENSET</name>
<description>Interrupt enable set register.</description>
<addressOffset>0x304</addressOffset>
<fields>
<field>
<name>HFCLKSTARTED</name>
<description>Enable interrupt on HFCLKSTARTED event.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>Disabled</name>
<description>Interrupt disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Interrupt enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
<description>Enable interrupt on write.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LFCLKSTARTED</name>
<description>Enable interrupt on LFCLKSTARTED event.</description>
<lsb>1</lsb> <msb>1</msb>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>Disabled</name>
<description>Interrupt disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Interrupt enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
<description>Enable interrupt on write.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DONE</name>
<description>Enable interrupt on DONE event.</description>
<lsb>3</lsb> <msb>3</msb>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>Disabled</name>
<description>Interrupt disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Interrupt enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
<description>Enable interrupt on write.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTTO</name>
<description>Enable interrupt on CTTO event.</description>
<lsb>4</lsb> <msb>4</msb>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>Disabled</name>
<description>Interrupt disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Interrupt enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
<description>Enable interrupt on write.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INTENCLR</name>
<description>Interrupt enable clear register.</description>
<addressOffset>0x308</addressOffset>
<fields>
<field>
<name>HFCLKSTARTED</name>
<description>Disable interrupt on HFCLKSTARTED event.</description>
<lsb>0</lsb> <msb>0</msb>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>Disabled</name>
<description>Interrupt disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Interrupt enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
<description>Disable interrupt on write.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LFCLKSTARTED</name>
<description>Disable interrupt on LFCLKSTARTED event.</description>
<lsb>1</lsb> <msb>1</msb>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>Disabled</name>
<description>Interrupt disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Interrupt enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
<description>Disable interrupt on write.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DONE</name>
<description>Disable interrupt on DONE event.</description>
<lsb>3</lsb> <msb>3</msb>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>Disabled</name>
<description>Interrupt disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Interrupt enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
<description>Disable interrupt on write.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTTO</name>
<description>Disable interrupt on CTTO event.</description>
<lsb>4</lsb> <msb>4</msb>
<enumeratedValues>