diff --git a/plat/renesas/rcar/bl2_rcar_setup.c b/plat/renesas/rcar/bl2_rcar_setup.c
index fa1e2ae92b..270a4ef2da 100644
--- a/plat/renesas/rcar/bl2_rcar_setup.c
+++ b/plat/renesas/rcar/bl2_rcar_setup.c
@@ -871,6 +871,9 @@ void bl2_plat_set_bl33_ep_info(image_info_t *image,
 {
 	SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
 	bl33_ep_info->spsr = rcar_get_spsr_for_bl33_entry();
+#ifdef RCAR_BL33_ARG0
+	bl33_ep_info->args.arg0 = RCAR_BL33_ARG0;
+#endif
 }
 
 
diff --git a/plat/renesas/rcar/bl2_secure_setting.c b/plat/renesas/rcar/bl2_secure_setting.c
index 66772b4f89..3ab651f44d 100644
--- a/plat/renesas/rcar/bl2_secure_setting.c
+++ b/plat/renesas/rcar/bl2_secure_setting.c
@@ -122,11 +122,7 @@ static const struct {
 	/*        0: registers can be accessed from secure resource only. */
 	/* Bit 7: Life Cycle 0 slave ports. */
 	/*        0: registers can be accessed from secure resource only. */
-#if (LIFEC_DEBUG_TRACE_ENABLE == 1)
-	{SEC_SEL15,		0xFFFFFF7FU},
-#else
 	{SEC_SEL15,		0xFFFFFF3FU},
-#endif
 
 	/** Security group 0 attribute setting for master ports 0 */
 	/** Security group 1 attribute setting for master ports 0 */
@@ -256,13 +252,8 @@ static const struct {
 	/*        SecurityGroup3 */
 	/* Bit 6: TDBG (is described in Debug and Trace section) slave ports.*/
 	/*        SecurityGroup3 */
-#if (LIFEC_DEBUG_TRACE_ENABLE == 1)
-	{SEC_GRP0COND15,	0x00000080U},
-	{SEC_GRP1COND15,	0x00000080U},
-#else
 	{SEC_GRP0COND15,	0x000000C0U},
 	{SEC_GRP1COND15,	0x000000C0U},
-#endif
 
 	/** Security write protection attribute setting for slave ports 0 */
 	/*	{SEC_READONLY0,		0x00000000U},*/
diff --git a/plat/renesas/rcar/ddr/boot_init_dram.c b/plat/renesas/rcar/ddr/boot_init_dram.c
index 8918040c81..84d3074cb2 100644
--- a/plat/renesas/rcar/ddr/boot_init_dram.c
+++ b/plat/renesas/rcar/ddr/boot_init_dram.c
@@ -105,8 +105,10 @@ static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
 static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
 static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
 static uint32_t Pll3Mode;
+static uint32_t loop_max;
 #ifdef DDR_BACKUPMODE
 uint32_t ddrBackup;
+//#define DDR_BACKUPMODE_HALF		//for Half channel(ch0,1 only)
 #endif
 
 #ifdef ddr_qos_init_setting // only for non qos_init
@@ -114,7 +116,7 @@ uint32_t ddrBackup;
 #define BASE_SUB_SLOT_NUM		(0x6U)
 #define SUB_SLOT_CYCLE			(0x7EU)		//126
 #define QOSWT_WTSET0_CYCLE		((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)	//unit:ns
- 
+
 uint32_t get_refperiod(void)
 {
 	return QOSWT_WTSET0_CYCLE;
@@ -250,7 +252,7 @@ static void dbsc_regset(void);
 static void dbsc_regset_post(void);
 static uint32_t dfi_init_start(void);
 static void change_lpddr4_en(uint32_t mode);
-static uint32_t set_term_code(void) ;
+static uint32_t set_term_code(void);
 static void ddr_register_set(uint32_t ch);
 static inline uint32_t wait_freqchgreq(uint32_t assert);
 static inline void set_freqchgack(uint32_t assert);
@@ -340,7 +342,7 @@ static void pll3_set(uint32_t on, uint32_t high)
 
 	/* PLL3 enable */
 	dataL= CPG_MSTPCRM1_ZB3ST_BIT | mmio_read_32(CPG_MSTPCRM1);
-	cpg_write_32(CPG_MSTPCRM1,	dataL);			/* zb3 clk stop */
+	cpg_write_32(CPG_MSTPCRM1,	dataL);		/* zb3 clk stop */
 	dsb_sev();
 
 	/* PLL3 Restart */
@@ -414,9 +416,11 @@ static void pll3_control(uint32_t on)
 	if(on) {
 		pll3_set(1,1);
 		Pll3Mode=1;
+		loop_max=2;
 	} else {
 		pll3_set(1,0);
 		Pll3Mode=0;
+		loop_max=8;
 	}
 }
 
@@ -457,96 +461,13 @@ static void send_dbcmd(uint32_t cmd)
 /*******************************************************************************
  *	DDRPHY register access (raw)
  ******************************************************************************/
-#if 0
-// M3N only
 static uint32_t reg_ddrphy_read ( uint32_t phyno, uint32_t regadd)
 {
 	uint32_t val;
-	uint32_t loop_max,loop;
-
-	if(Pll3Mode)
-		loop_max=2;
-	else
-		loop_max=8;
-
-	mmio_write_32(DBSC_DBPDRGA(phyno), regadd|0x00004000);
-	dsb_sev();
-	while(mmio_read_32(DBSC_DBPDRGA(phyno))!=(regadd|0x0000C000)){dsb_sev();};
-	val = mmio_read_32(DBSC_DBPDRGA(phyno));
-	mmio_write_32(DBSC_DBPDRGA(phyno), regadd|0x00008000);
-	while(mmio_read_32(DBSC_DBPDRGA(phyno))!=regadd){dsb_sev();};
-	dsb_sev();
-
-	for(loop=0;loop<loop_max;loop++){
-		val = mmio_read_32(DBSC_DBPDRGD(phyno));
-		dsb_sev();
-	}
-	mmio_write_32(DBSC_DBPDRGA(phyno), regadd|0x00008000);
-	while(mmio_read_32(DBSC_DBPDRGA(phyno))!=regadd){dsb_sev();};
-
-	(void)val;
-	return val ;
-}
-
-static void reg_ddrphy_write ( uint32_t phyno, uint32_t regadd, uint32_t regdata)
-{
-	uint32_t val;
-	uint32_t loop_max,loop;
-
-	if(Pll3Mode)
-		loop_max=2;
-	else
-		loop_max=8;
-
-	mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
-	dsb_sev();
-	while(mmio_read_32(DBSC_DBPDRGA(phyno))!=regadd){dsb_sev();};
-	for(loop=0;loop<loop_max;loop++){
-		val = mmio_read_32(DBSC_DBPDRGD(phyno));
-		dsb_sev();
-	}
-	mmio_write_32(DBSC_DBPDRGD(phyno),regdata);
-	dsb_sev();
-	for(loop=0;loop<loop_max;loop++){
-		val = mmio_read_32(DBSC_DBPDRGD(phyno));
-		dsb_sev();
-	}
-	while(mmio_read_32(DBSC_DBPDRGA(phyno))!=(regadd|0x00008000)){dsb_sev();};
-	mmio_write_32(DBSC_DBPDRGA(phyno), regadd|0x00008000);
-	while(mmio_read_32(DBSC_DBPDRGA(phyno))!=regadd){dsb_sev();};
-	(void)val;
-}
-
-static void reg_ddrphy_write_a ( uint32_t regadd, uint32_t regdata)
-{
-	uint32_t ch;
-	foreach_vch(ch) {
-		reg_ddrphy_write ( ch, regadd, regdata);
-		dsb_sev();
-	}
-
-}
-
-static inline void ddrphy_regif_idle()
-{
-	uint32_t val;
-	val = reg_ddrphy_read(0,ddr_regdef_adr(_reg_PI_INT_STATUS));
-	dsb_sev();
-	(void)val;
-
-}
-#else
-static uint32_t reg_ddrphy_read ( uint32_t phyno, uint32_t regadd)
-{
-	uint32_t val;
-	uint32_t loop_max,loop;
-
-	if (PRR_PRODUCT_M3N!=Prr_Product) {
-		if(Pll3Mode)
-			loop_max=2;
-		else
-			loop_max=8;
+	uint32_t loop;
 
+	val = 0;
+	if ((PRR_PRODUCT_M3N!=Prr_Product)&&(PRR_PRODUCT_V3H!=Prr_Product)) {
 		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
 		dsb_sev();
 
@@ -561,11 +482,6 @@ static uint32_t reg_ddrphy_read ( uint32_t phyno, uint32_t regadd)
 		}
 		(void)val;
 	}else{
-		if(Pll3Mode)
-			loop_max=2;
-		else
-			loop_max=8;
-
 		mmio_write_32(DBSC_DBPDRGA(phyno), regadd|0x00004000);
 		dsb_sev();
 		while(mmio_read_32(DBSC_DBPDRGA(phyno))!=(regadd|0x0000C000)){dsb_sev();};
@@ -574,28 +490,23 @@ static uint32_t reg_ddrphy_read ( uint32_t phyno, uint32_t regadd)
 		while(mmio_read_32(DBSC_DBPDRGA(phyno))!=regadd){dsb_sev();};
 		dsb_sev();
 
-		for(loop=0;loop<loop_max;loop++){
-			val = mmio_read_32(DBSC_DBPDRGD(phyno));
-			dsb_sev();
-		}
 		mmio_write_32(DBSC_DBPDRGA(phyno), regadd|0x00008000);
 		while(mmio_read_32(DBSC_DBPDRGA(phyno))!=regadd){dsb_sev();};
+
+		dsb_sev();
+		val = mmio_read_32(DBSC_DBPDRGD(phyno));
+		dsb_sev();
 		(void)val;
 	}
-	return val ;
+	return val;
 }
 
 static void reg_ddrphy_write ( uint32_t phyno, uint32_t regadd, uint32_t regdata)
 {
 	uint32_t val;
-	uint32_t loop_max,loop;
-
-	if (PRR_PRODUCT_M3N!=Prr_Product) {
-		if(Pll3Mode)
-			loop_max=2;
-		else
-			loop_max=8;
+	uint32_t loop;
 
+	if ((PRR_PRODUCT_M3N!=Prr_Product)&&(PRR_PRODUCT_V3H!=Prr_Product)) {
 		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
 		dsb_sev();
 		for(loop=0;loop<loop_max;loop++){
@@ -610,27 +521,22 @@ static void reg_ddrphy_write ( uint32_t phyno, uint32_t regadd, uint32_t regdata
 			dsb_sev();
 		}
 	}else{
-		if(Pll3Mode)
-			loop_max=2;
-		else
-			loop_max=8;
-
 		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
 		dsb_sev();
+
 		while(mmio_read_32(DBSC_DBPDRGA(phyno))!=regadd){dsb_sev();};
-		for(loop=0;loop<loop_max;loop++){
-			val = mmio_read_32(DBSC_DBPDRGD(phyno));
-			dsb_sev();
-		}
+		dsb_sev();
+
 		mmio_write_32(DBSC_DBPDRGD(phyno),regdata);
 		dsb_sev();
-		for(loop=0;loop<loop_max;loop++){
-			val = mmio_read_32(DBSC_DBPDRGD(phyno));
-			dsb_sev();
-		}
+
 		while(mmio_read_32(DBSC_DBPDRGA(phyno))!=(regadd|0x00008000)){dsb_sev();};
 		mmio_write_32(DBSC_DBPDRGA(phyno), regadd|0x00008000);
+
 		while(mmio_read_32(DBSC_DBPDRGA(phyno))!=regadd){dsb_sev();};
+		dsb_sev();
+
+		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
 	}
 	(void)val;
 }
@@ -639,21 +545,14 @@ static void reg_ddrphy_write_a ( uint32_t regadd, uint32_t regdata)
 {
 	uint32_t ch;
 	uint32_t val;
-	uint32_t loop_max,loop;
-
-	if (PRR_PRODUCT_M3N!=Prr_Product) {
-		if(Pll3Mode)
-			loop_max=2;
-		else
-			loop_max=8;
+	uint32_t loop;
 
+	if ((PRR_PRODUCT_M3N!=Prr_Product)&&(PRR_PRODUCT_V3H!=Prr_Product)) {
 		foreach_vch(ch) {
 			mmio_write_32(DBSC_DBPDRGA(ch), regadd);
-		dsb_sev();
+			dsb_sev();
 		}
 
-		dsb_sev();
-
 		foreach_vch(ch) {
 			mmio_write_32(DBSC_DBPDRGD(ch),regdata);
 			dsb_sev();
@@ -680,8 +579,6 @@ static inline void ddrphy_regif_idle()
 	(void)val;
 }
 
-#endif
-
 /*******************************************************************************
  *	DDRPHY register access (field modify)
  ******************************************************************************/
@@ -889,8 +786,8 @@ static uint32_t ddrphy_regif_chk(void)
 
 	if ((PRR_PRODUCT_H3==Prr_Product) && (PRR_PRODUCT_11< Prr_Cut)) {
 		PI_VERSION_CODE=0x2040;		// H3ver2.0
-	} else if (PRR_PRODUCT_M3N==Prr_Product) {
-		PI_VERSION_CODE=0x2040;		// M3Nver1.0
+	} else if ((PRR_PRODUCT_M3N==Prr_Product)||(PRR_PRODUCT_V3H==Prr_Product)) {
+		PI_VERSION_CODE=0x2040;		// M3Nver1.0/V3H
 	} else {
 		PI_VERSION_CODE=0x2041;		// H3ver1.x/M3ver1.x
 	}
@@ -1188,6 +1085,7 @@ static void regif_pll_wa(void)
 			 ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_PLL_CTRL));
 
 	} else {
+		// PLL setting for PHY : M3,M3N/H3ver2
 		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT) ,(0x5064<<ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
 
 		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
@@ -1369,7 +1267,7 @@ static void ddrtbl_load(void)
 
 		DDR_PHY_ADR_I_NUM=2;
 	} else {
-	// M3N ver1.0
+	// M3N ver1.0 , V3H ver1.0
 		_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
 			DDR_PHY_SLICE_REGSET_M3N, DDR_PHY_SLICE_REGSET_NUM_M3N);
 		_tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
@@ -1409,7 +1307,7 @@ static void ddrtbl_load(void)
 	}
 
 	/***********************************************************************
- 	PM3ver1.0 vref w/ax
+	PM3ver1.0 vref w/a
 	***********************************************************************/
 	if ((PRR_PRODUCT_H3==Prr_Product) && (PRR_PRODUCT_10==Prr_Cut) && (Boardcnf->phyvalid==0x05)) {
 		ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_VREF_CTRL_DQ_0, 0x0f02);
@@ -1420,7 +1318,7 @@ static void ddrtbl_load(void)
 	}
 
 	/***********************************************************************
-	ON FLY GATE ADJUST
+	on fly gate adjust
 	***********************************************************************/
 	if ((PRR_PRODUCT_M3==Prr_Product) && (PRR_PRODUCT_10== Prr_Cut)) {
 		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_ON_FLY_GATE_ADJUST_EN, 0);
@@ -1561,18 +1459,18 @@ static void ddr_config_sub(void)
 	***********************************************************************/
 		const uint32_t _par_CALVL_DEVICE_MAP=1;
 		dataL = Boardcnf->ch[ch].ca_swap | 0x00888888;
+
 		/* --- ADR_CALVL_SWIZZLE --- */
-		if (((PRR_PRODUCT_H3==Prr_Product) && (PRR_PRODUCT_11< Prr_Cut))
-		    |(PRR_PRODUCT_M3N==Prr_Product)) {
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
-			ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP);
-		} else {
+		if (PRR_PRODUCT_M3==Prr_Product) {
 			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL);
 			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000);
 			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL);
 			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000);
 			ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP);
+		} else {
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
+			ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP);
 		}
 
 		/* --- ADR_ADDR_SEL --- */
@@ -1591,12 +1489,17 @@ static void ddr_config_sub(void)
 	/***********************************************************************
 		BOARD SETTINGS (BYTE_ORDER_SEL)
 	***********************************************************************/
-		dataL=0;
-		tmp=Boardcnf->ch[ch].dqs_swap;
-
-		if (((PRR_PRODUCT_H3==Prr_Product) && (PRR_PRODUCT_11< Prr_Cut))
-		    |(PRR_PRODUCT_M3N==Prr_Product)) {
-			dataL = tmp;
+		if(PRR_PRODUCT_M3==Prr_Product) {
+			/* --- DATA_BYTE_SWAP --- */
+			dataL=0;
+			tmp=Boardcnf->ch[ch].dqs_swap;
+			for(i=0;i<4;i++){
+				dataL |= ((tmp&0x3)<<(i*2));
+				tmp = tmp>>4;
+			}
+		} else {
+			/* --- DATA_BYTE_SWAP --- */
+			dataL = Boardcnf->ch[ch].dqs_swap;
 			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 1);
 			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, (dataL       ) & 0x0f );
 			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, (dataL >> 4*1) & 0x0f );
@@ -1604,11 +1507,6 @@ static void ddr_config_sub(void)
 			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, (dataL >> 4*3) & 0x0f );
 
 			ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x0);
-		} else {
-			for(i=0;i<4;i++){
-				dataL |= ((tmp&0x3)<<(i*2));
-				tmp = tmp>>4;
-			}
 		}
 		ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, dataL);
 	}
@@ -1641,12 +1539,13 @@ static void ddr_config_sub_h3v1x(void)
 	uint32_t dataL;
 	uint32_t tmp;
 	uint8_t high_byte[SLICE_CNT];
+
 	foreach_vch(ch){
 		uint32_t ca_swizzle;
 		uint32_t ca;
 		uint32_t csmap;
 	/***********************************************************************
-	BOARD SETTINGS (DQ,DM,VREF_DRIVING)
+		BOARD SETTINGS (DQ,DM,VREF_DRIVING)
 	***********************************************************************/
 		csmap=0;
 		for(slice=0;slice<SLICE_CNT;slice++){
@@ -1664,7 +1563,7 @@ static void ddr_config_sub_h3v1x(void)
 			}
 		}
 	/***********************************************************************
-	BOARD SETTINGS (CA,ADDR_SEL)
+		BOARD SETTINGS (CA,ADDR_SEL)
 	***********************************************************************/
 		ca=Boardcnf->ch[ch].ca_swap;
 		ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca);
@@ -1853,14 +1752,14 @@ static void dbsc_regset_pre(void)
 	if(PRR_PRODUCT_M3==Prr_Product) {
 		dataL = 0xe4e4e4e4;
 		foreach_ech(ch) {
-			if((Boardcnf->phyvalid & (1<<ch)))
+			if((ddr_phyvalid & (1<<ch)))
 				dataL = (dataL &(~(0x000000FF << (ch*8))))
 					|((	  (Boardcnf->ch[ch].dqs_swap & 0x0003)
 						|((Boardcnf->ch[ch].dqs_swap & 0x0030) >> 2)
 						|((Boardcnf->ch[ch].dqs_swap & 0x0300) >> 4)
 						|((Boardcnf->ch[ch].dqs_swap & 0x3000) >> 6)	)<< (ch*8));
 		}
-		mmio_write_32(DBSC_DBBCAMSWAP, dataL);
+		mmio_write_32(DBSC_DBBSWAP, dataL);
 	}
 }
 
@@ -2120,11 +2019,11 @@ static void dbsc_regset_post(void)
 	uint32_t ch,cs;
 	uint32_t dataL;
 	uint32_t	slice,rdlat_max;
-	rdlat_max = 0 ;
+	rdlat_max = 0;
 	foreach_vch(ch){
 		for(slice=0;slice<SLICE_CNT;slice++){
 			dataL = ddr_getval_s(ch, slice,	_reg_PHY_RDDQS_LATENCY_ADJUST);
-			if(dataL>rdlat_max) rdlat_max = dataL ;
+			if(dataL>rdlat_max) rdlat_max = dataL;
 		}
 	}
 	mmio_write_32(DBSC_DBTR(24),
@@ -2154,7 +2053,7 @@ static void dbsc_regset_post(void)
 		reg_ddrphy_write_a(0x00001010,	0x01000000);
 
 	/*set REFCYCLE */
-	dataL = (get_refperiod())*ddr_mbps/2000/ddr_mbpsdiv ;
+	dataL = (get_refperiod())*ddr_mbps/2000/ddr_mbpsdiv;
 
 	mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL&0xffff));
 	mmio_write_32(DBSC_DBRFCNF2, 0x00010000|DBSC_REFINTS);
@@ -2165,13 +2064,55 @@ static void dbsc_regset_post(void)
 
 #ifdef DDR_BACKUPMODE
 	if(ddrBackup==DRAM_BOOT_STATUS_WARM){
+#ifdef DDR_BACKUPMODE_HALF		//for Half channel(ch0,1 only)
+		PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ",1);
+		send_dbcmd(0x08040001);
+			//bit27-24:OPC[3:0]   = 1000 : PD(Power Down Entry/Exit)
+			//bit23-20:CH[3:0]    = 0000 : channel 0
+			//bit18-16:RANK[2:0]  = 100  : All ranks
+			//bit15-0:ARG[15:0]   = 1    : Power Down Exit
+		wait_dbcmd();
+		send_dbcmd(0x0A040001);
+			//bit27-24:OPC[3:0]   = 1010 : SR(Self-Refresh Entry/Exit)
+			//bit23-20:CH[3:0]    = 0000 : channel 0
+			//bit18-16:RANK[2:0]  = 100  : All ranks
+			//bit15-0:ARG[15:0]   = 1    : Self-Refresh Exit
+		wait_dbcmd();
+		send_dbcmd(0x04040010);
+			//bit27-24:OPC[3:0]   = 0100 : PreA(Precharge All)
+			//bit23-20:CH[3:0]    = 0000 : channel 0
+			//bit18-16:RANK[2:0]  = 100  : All ranks
+			//bit15-0:ARG[15:0]   = 0x10 : Don't set avalue other than H'0010.
+		wait_dbcmd();
+
+		if (PRR_PRODUCT_H3==Prr_Product) {
+			send_dbcmd(0x08140001);
+				//bit27-24:OPC[3:0]   = 1000 : PD(Power Down Entry/Exit)
+				//bit23-20:CH[3:0]    = 0001 : channel 1
+				//bit18-16:RANK[2:0]  = 100  : All ranks
+				//bit15-0:ARG[15:0]   = 1    : Power Down Exit
+			wait_dbcmd();
+			send_dbcmd(0x0A140001);
+				//bit27-24:OPC[3:0]   = 1010 : SR(Self-Refresh Entry/Exit)
+				//bit23-20:CH[3:0]    = 0001 : channel 1
+				//bit18-16:RANK[2:0]  = 100  : All ranks
+				//bit15-0:ARG[15:0]   = 1    : Self-Refresh Exit
+			wait_dbcmd();
+			send_dbcmd(0x04140010);
+				//bit27-24:OPC[3:0]   = 0100 : PreA(Precharge All)
+				//bit23-20:CH[3:0]    = 0001 : channel 1
+				//bit18-16:RANK[2:0]  = 100  : All ranks
+				//bit15-0:ARG[15:0]   = 0x10 : Don't set avalue other than H'0010.
+			wait_dbcmd();
+		}
+#else							//for All channels
 		send_dbcmd(0x08840001);
 		wait_dbcmd();
 		send_dbcmd(0x0A840001);
 		wait_dbcmd();
-
 		send_dbcmd(0x04840010);
 		wait_dbcmd();
+#endif//DDR_BACKUPMODE_HALF
 	}
 #endif//DDR_BACKUPMODE
 
@@ -2558,7 +2499,6 @@ static uint32_t pi_training_go(void)
 	foreach_vch(ch)
 		ddr_getval( ch, _reg_PI_INT_STATUS);
 
-
 	/* set dfi_phymstr_ack = 1 */
 	mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001);
 	dsb_sev();
@@ -2644,7 +2584,7 @@ static uint32_t init_ddr(void)
 	dsb_sev();
 
 	if ((((PRR_PRODUCT_H3==Prr_Product) && (PRR_PRODUCT_11<Prr_Cut))
-	    |(PRR_PRODUCT_M3N==Prr_Product)) && (Boardcnf->dbi_en))
+	    |(PRR_PRODUCT_M3N==Prr_Product)|(PRR_PRODUCT_V3H==Prr_Product)) && (Boardcnf->dbi_en))
 		reg_ddrphy_write_a(0x00001010, 0x01000001);
 	else
 		reg_ddrphy_write_a(0x00001010, 0x00000001);
@@ -2719,7 +2659,7 @@ static uint32_t init_ddr(void)
 	/***********************************************************************
 	rx offset calibration
 	***********************************************************************/
-	if ((PRR_PRODUCT_11< Prr_Cut)|(PRR_PRODUCT_M3N==Prr_Product))
+	if ((PRR_PRODUCT_11< Prr_Cut)|(PRR_PRODUCT_M3N==Prr_Product)|(PRR_PRODUCT_V3H==Prr_Product))
 		err = rx_offset_cal_hw();
 	else
 		err = rx_offset_cal();
@@ -2835,6 +2775,7 @@ static uint32_t init_ddr(void)
 	/***********************************************************************
 	RDQLVL Training
 	***********************************************************************/
+	ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x1);
 	err=rdqdm_man();
 	if(err) {
 		return(INITDRAM_ERR_T);
@@ -2857,7 +2798,7 @@ static uint32_t init_ddr(void)
 	update_dly();
 	MSG_LF("init_ddr:11\n");
 	if (((PRR_PRODUCT_H3==Prr_Product) && (PRR_PRODUCT_11<Prr_Cut))
-	    |(PRR_PRODUCT_M3N==Prr_Product)) {
+	    |(PRR_PRODUCT_M3N==Prr_Product)|(PRR_PRODUCT_V3H==Prr_Product)) {
 		ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY,0x0);
 		ddr_setval_ach(_reg_PI_DFI40_POLARITY,0x0);
 	}
@@ -2874,7 +2815,6 @@ static uint32_t init_ddr(void)
 /*******************************************************************************
  *	SW LEVELING COMMON
  ******************************************************************************/
-
 static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
 {
 	uint32_t ch;
@@ -2888,6 +2828,8 @@ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
 	err=0;
 	/* set EXIT -> OP_DONE is cleared */
 	ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x1);
+	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, 0);
+
 	/* kick */
 	foreach_vch(ch){
 		if(ch_have_this_cs[ddr_csn%2] & (1<<ch)){
@@ -3367,13 +3309,8 @@ static uint32_t rdqdm_man(void)
 
 	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
 		0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,_reg_PHY_DQ_TSEL_ENABLE));
-#ifdef debug_wdqext	// NON
-	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
-		0x00000004 | 0x00000001);
-#else
 	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
 		0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,_reg_PHY_DQS_TSEL_ENABLE));
-#endif
 	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
 		0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,_reg_PHY_DQ_TSEL_SELECT));
 	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
@@ -3387,13 +3324,8 @@ static uint32_t rdqdm_man(void)
 
 	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
 		ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,_reg_PHY_DQ_TSEL_ENABLE));
-#ifdef debug_wdqext	// NON
-	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
-		0x00000000 | 0x00000001);
-#else
 	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
 		ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,_reg_PHY_DQS_TSEL_ENABLE));
-#endif
 	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
 		ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,_reg_PHY_DQ_TSEL_SELECT));
 	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
@@ -3532,6 +3464,7 @@ static uint32_t rx_offset_cal_hw(void) {
 	uint32_t complete;
 	uint32_t tmp;
 	uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
+
 	ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x1);
 	ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x0);
 	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x0);
@@ -3678,7 +3611,22 @@ int32_t InitDram(void)
 		return 0xff;
 	}
 	Boardcnf = (struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
+
+//RCAR_DRAM_SPLIT_2CH		(2U)
+#if RCAR_DRAM_SPLIT == 2
+	/***********************************************************************
+	PM3ver1.x ch swap for 2ch-split
+	***********************************************************************/
+	if ((PRR_PRODUCT_H3==Prr_Product) && (Boardcnf->phyvalid==0x05)) {
+		mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006);
+		ddr_phyvalid = 0x03;
+	} else {
+		ddr_phyvalid = Boardcnf->phyvalid;
+	}
+#else//RCAR_DRAM_SPLIT_2CH
 	ddr_phyvalid = Boardcnf->phyvalid;
+#endif//RCAR_DRAM_SPLIT_2CH
+
 	max_density=0;
 	max_cs=0;
 	for(cs=0;cs<CS_CNT;cs++){
@@ -3820,8 +3768,6 @@ void pvtcode_update2(void){
 	}
 }
 
-/* --------------------------------------------------------------------------- */
-// thermal
 void ddr_padcal_tcompensate_getinit(uint32_t override)
 {
 	uint32_t ch;
@@ -3871,7 +3817,7 @@ void ddr_padcal_tcompensate_getinit(uint32_t override)
 // for QoS init
 uint8_t get_boardcnf_phyvalid(void)
 {
-	return Boardcnf->phyvalid ;
+	return Boardcnf->phyvalid;
 }
 #endif//ddr_qos_init_setting
 
diff --git a/plat/renesas/rcar/ddr/boot_init_dram_config.c b/plat/renesas/rcar/ddr/boot_init_dram_config.c
index 77d8d9b7dc..b475e7b1a2 100644
--- a/plat/renesas/rcar/ddr/boot_init_dram_config.c
+++ b/plat/renesas/rcar/ddr/boot_init_dram_config.c
@@ -33,7 +33,7 @@
  *	NUMBER OF BOARD CONFIGRATION
  *	PLEASE DEFINE
  ******************************************************************************/
-#define BOARDNUM 13
+#define BOARDNUM 15
 /*******************************************************************************
  *	PLEASE SET board number or board judge function
  ******************************************************************************/
@@ -332,11 +332,11 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 /*ch[0]*/	{
 /*ddr_density[]*/	{ 0x02, 0xFF },    // M3SIP(8G bit 1rank)
 /*ca_swap*/		0x00543210U,
-/*dqs_swap*/		0x3201U,
+/*dqs_swap*/		0x3201,
 /*dq_swap[]*/		{ 0x70612543, 0x43251670, 0x45326170, 0x10672534 },
 /*dm_swap[]*/		{ 0x08, 0x08, 0x08, 0x08 },
 /*wdqlvl_patt[]*/	WDQLVL_PAT,
-/*cacs_adj*/		{ -1, 0, 0, 0, 0, 0, 0, 0,
+/*cacs_adj*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
 			  0, 0 },
 /*dm_adj_w*/		{ 0, 0, 0, 0 },
 /*dqdm_adj_w*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
@@ -898,8 +898,6 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 {
 	0x01,		/* phyvalid */
 	0x01,		/* dbi_en */
-//	0x280,		/* cacs_dly */
-//	0x2c0,		/* cacs_dly */
 	0x300,		/* cacs_dly */
 	0,		/* cacs_dly_adj */
 	0x300,		/* dqdm_dly_w */
@@ -933,7 +931,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
  */
 {
 	0x01,		/* phyvalid */
-	0x01,		/* dbi_en */
+	0x1,		/* dbi_en */
 	0x300,		/* cacs_dly */
 	0,		/* cacs_dly_adj */
 	0x300,		/* dqdm_dly_w */
@@ -961,6 +959,132 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 		}
 	}
 },
+/*
+ * boardcnf[12] RENESAS CONDOR board w V3H
+ */
+{
+	0x01,		/* phyvalid */
+	0x1,		/* dbi_en */
+	0x300,		/* cacs_dly */
+	0,		/* cacs_dly_adj */
+	0x300,		/* dqdm_dly_w */
+	0x0a0,		/* dqdm_dly_r */
+	{
+/*ch[0]*/	{
+/*ddr_density[]*/	{ 0x02, 0x02 },
+/*ca_swap*/		0x00501342 ,
+/*dqs_swap*/		0x3201 ,
+/*dq_swap[]*/		{ 0x70562134, 0x34526071, 0x23147506, 0x12430567 },
+/*dm_swap[]*/		{ 0x08, 0x08, 0x08, 0x08 },
+/*wdqlvl_patt[]*/	WDQLVL_PAT,
+/*cacs_adj*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0 },
+/*dm_adj_w*/		{ 0, 0, 0, 0 },
+/*dqdm_adj_w*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0 },
+/*dm_adj_r*/		{ 0, 0, 0, 0 },
+/*dqdm_adj_r*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0 }
+		}
+	}
+},
+/*
+ * boardcnf[13] RENESAS KRIEK board w PM3
+ */
+{
+	0x05,		/* phyvalid */
+	0x00,		/* dbi_en */
+	0x2c0,		/* cacs_dly */
+	-320,		/* cacs_dly_adj */
+	0x300,		/* dqdm_dly_w */
+	0x0a0,		/* dqdm_dly_r */
+	{
+/*ch[0]*/	{
+/*ddr_density[]*/	{ 0x02, 0x02 },
+/*ca_swap*/		0x00345201,
+/*dqs_swap*/		0x3201,
+/*dq_swap[]*/		{ 0x01672543, 0x45361207, 0x45632107, 0x60715234 },
+/*dm_swap[]*/		{ 0x08, 0x08, 0x08, 0x08 },
+/*wdqlvl_patt[]*/	WDQLVL_PAT,
+/*cacs_adj*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0 },
+/*dm_adj_w*/		{ 0, 0, 0, 0 },
+/*dqdm_adj_w*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0 },
+/*dm_adj_r*/		{ 0, 0, 0, 0 },
+/*dqdm_adj_r*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0 }
+		},
+/*ch[1]*/	{	// for DRAM_SPLIT_2CH
+/*ddr_density[]*/	{ 0x02, 0x02 },
+/*ca_swap*/		0x00302154,
+/*dqs_swap*/		0x2310,
+/*dq_swap[]*/		{ 0x01672543, 0x45361207, 0x45632107, 0x60715234 },
+/*dm_swap[]*/		{ 0x08, 0x08, 0x08, 0x08 },
+/*wdqlvl_patt[]*/	WDQLVL_PAT,
+/*cacs_adj*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0 },
+/*dm_adj_w*/		{ 0, 0, 0, 0 },
+/*dqdm_adj_w*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0 },
+/*dm_adj_r*/		{ 0, 0, 0, 0 },
+/*dqdm_adj_r*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0 }
+		},
+/*ch[2]*/	{	// for DRAM_SPLIT_NON
+/*ddr_density[]*/	{ 0x02, 0x02 },
+/*ca_swap*/		0x00302154,
+/*dqs_swap*/		0x2310,
+/*dq_swap[]*/		{ 0x01672543, 0x45361207, 0x45632107, 0x60715234 },
+/*dm_swap[]*/		{ 0x08, 0x08, 0x08, 0x08 },
+/*wdqlvl_patt[]*/	WDQLVL_PAT,
+/*cacs_adj*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0 },
+/*dm_adj_w*/		{ 0, 0, 0, 0 },
+/*dqdm_adj_w*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0 },
+/*dm_adj_r*/		{ 0, 0, 0, 0 },
+/*dqdm_adj_r*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0 }
+		},
+/*ch[3]*/	{ // Dummy
+/*ddr_density[]*/	{ 0xff, 0xff },
+/*ca_swap*/		0,
+/*dqs_swap*/		0,
+/*dq_swap[]*/		{ 0, 0, 0, 0 },
+/*dm_swap[]*/		{ 0, 0, 0, 0 },
+/*wdqlvl_patt[]*/	WDQLVL_PAT,
+/*cacs_adj*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0 },
+/*dm_adj_w*/		{ 0, 0, 0, 0 },
+/*dqdm_adj_w*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0 },
+/*dm_adj_r*/		{ 0, 0, 0, 0 },
+/*dqdm_adj_r*/		{ 0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0 }
+		}
+	}
+}
 };
 /*******************************************************************************
  *	EXTAL CLOCK DEFINITION
@@ -1165,13 +1289,20 @@ static uint32_t _board_judge(void) {
 	usb2_ovc_open = opencheck_SSI_WS6();
 
 	/* RENESAS Eva-borad */
-	if(usb2_ovc_open) {
+	if(PRR_PRODUCT_V3H == Prr_Product) {
+		/* RENESAS Condor board */
+		brd = 12;
+	}
+	else if(usb2_ovc_open) {
 		if(PRR_PRODUCT_M3N == Prr_Product) {
-			/* RENESAS Kriek board */
+			/* RENESAS Kriek board (M3N)*/
 			brd = 10;
-		} else {
-			/* RENESAS Kriek board */
+		} else if(PRR_PRODUCT_M3 == Prr_Product) {
+			/* RENESAS Kriek board (M3)*/
 			brd = 1;
+		} else {
+			/* RENESAS Kriek board (PM3)*/
+			brd = 13;
 		}
 	} else {
 		if(PRR_PRODUCT_H3 == Prr_Product) {
@@ -1182,14 +1313,12 @@ static uint32_t _board_judge(void) {
 			/* RENESAS SALVATOR-X (H3SIP_VER2.0) */
 			brd = 7;
 		  }
+		} else 	if(PRR_PRODUCT_M3N == Prr_Product) {
+			/* RENESAS SALVATOR-X (M3N-SIP) */
+			brd = 11;
 		} else {
-			if(PRR_PRODUCT_M3N == Prr_Product) {
-				/* RENESAS SALVATOR-X (M3N-SIP) */
-				brd = 11;
-			  } else {
-				/* RENESAS SALVATOR-X (M3-SIP) */
-				brd = 0;
-			}
+			/* RENESAS SALVATOR-X (M3-SIP) */
+			brd = 0;
 		}
 	}
 #endif//(RCAR_GEN3_ULCB==1)
diff --git a/plat/renesas/rcar/ddr/boot_init_dram_regdef.h b/plat/renesas/rcar/ddr/boot_init_dram_regdef.h
index aed5b9eea7..5ae7c3f6aa 100644
--- a/plat/renesas/rcar/ddr/boot_init_dram_regdef.h
+++ b/plat/renesas/rcar/ddr/boot_init_dram_regdef.h
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#define RCAR_DDR_VERSION        "rev.0.28rc03"
+#define RCAR_DDR_VERSION        "rev.0.28"
 #define DRAM_CH_CNT		0x04
 #define SLICE_CNT		0x04
 #define CS_CNT			0x02
@@ -156,8 +156,8 @@
 #define DBSC_DBODT(x)		(0xE6790460U+0x4*(x))
 #define DBSC_DBADJ0		0xE6790500U
 #define DBSC_DBDBICNT		0xE6790518U
-
 #define DBSC_DBDFIPMSTRCNF	0xE6790520U
+#define DBSC_DBDFICUPDCNF	0xE679052CU
 
 #define DBSC_DBPDLK(ch)		(0xE6790620U+0x40U*(ch))
 #define DBSC_DBPDLK_0		0xE6790620U
@@ -212,7 +212,7 @@
 #define DBSC_DBCAM0CNF1		0xE6790904U
 #define DBSC_DBCAM0CNF2		0xE6790908U
 #define DBSC_DBCAM0CNF3		0xE679090CU
-#define DBSC_DBBCAMSWAP		0xE67909F0U
+#define DBSC_DBBSWAP		0xE67909F0U
 #define DBSC_DBBCAMDIS		0xE67909FCU
 #define DBSC_DBSCHCNT0		0xE6791000U
 #define DBSC_DBSCHCNT1		0xE6791004U
@@ -234,6 +234,7 @@
 #define DBSC_SCFCTST1		0xE6791708U
 #define DBSC_SCFCTST2		0xE679170CU
 
+#define DBSC_DBMRRDR(chab)	(0xE6791800U+0x4U*(chab))
 #define DBSC_DBMRRDR_0		0xE6791800U
 #define DBSC_DBMRRDR_1		0xE6791804U
 #define DBSC_DBMRRDR_2		0xE6791808U
@@ -242,7 +243,6 @@
 #define DBSC_DBMRRDR_5		0xE679180CU
 #define DBSC_DBMRRDR_6		0xE679180CU
 #define DBSC_DBMRRDR_7		0xE679180CU
-#define DBSC_DBMRRDR(chab)	(0xE6791800U+0x4U*(chab))
 
 #define DBSC_DBMEMSWAPCONF0	0xE6792000U
 
@@ -266,7 +266,6 @@
 #define DBSC_DFI_FREQ_2		0xE6790694U
 #define DBSC_DFI_FREQ_3		0xE67906D4U
 
-
 /* STAT registers */
 #define MSTAT_SL_INIT		0xE67E8000
 #define MSTAT_REF_ARS		0xE67E8004
@@ -297,41 +296,32 @@
 #define CPG_MSTPSR5		0xE615003C	// R	32	Module stop status register 5
 #define CPG_SMSTPCR5		0xE6150144	// R/W	32	System module stop control register 5
 
-/* DBSC naisho??? */
-//#define DBSC_DBSTATE0		0xE6790108U
-//#define DBSC_DBADJ2		0xE6790508U
-
-#define DBSC_DBDFICUPDCNF	0xE679052CU
-#define DBSC_DBCAM0CNF0		0xE6790900U
-
-
-/////
-#define	DBSC_BASE					(0xE6790000U)
-#define DBSC_DBSCHQOS00				(DBSC_BASE + 0x1030U)
-#define DBSC_DBSCHQOS01				(DBSC_BASE + 0x1034U)
-#define DBSC_DBSCHQOS02				(DBSC_BASE + 0x1038U)
-#define DBSC_DBSCHQOS03				(DBSC_BASE + 0x103CU)
-#define DBSC_DBSCHQOS40				(DBSC_BASE + 0x1070U)
-#define DBSC_DBSCHQOS41				(DBSC_BASE + 0x1074U)
-#define DBSC_DBSCHQOS42				(DBSC_BASE + 0x1078U)
-#define DBSC_DBSCHQOS43				(DBSC_BASE + 0x107CU)
-#define DBSC_DBSCHQOS90				(DBSC_BASE + 0x10C0U)
-#define DBSC_DBSCHQOS91				(DBSC_BASE + 0x10C4U)
-#define DBSC_DBSCHQOS92				(DBSC_BASE + 0x10C8U)
-#define DBSC_DBSCHQOS93				(DBSC_BASE + 0x10CCU)
-#define DBSC_DBSCHQOS120			(DBSC_BASE + 0x10F0U)
-#define DBSC_DBSCHQOS121			(DBSC_BASE + 0x10F4U)
-#define DBSC_DBSCHQOS122			(DBSC_BASE + 0x10F8U)
-#define DBSC_DBSCHQOS123			(DBSC_BASE + 0x10FCU)
-#define DBSC_DBSCHQOS130			(DBSC_BASE + 0x1100U)
-#define DBSC_DBSCHQOS131			(DBSC_BASE + 0x1104U)
-#define DBSC_DBSCHQOS132			(DBSC_BASE + 0x1108U)
-#define DBSC_DBSCHQOS133			(DBSC_BASE + 0x110CU)
-#define DBSC_DBSCHQOS140			(DBSC_BASE + 0x1110U)
-#define DBSC_DBSCHQOS141			(DBSC_BASE + 0x1114U)
-#define DBSC_DBSCHQOS142			(DBSC_BASE + 0x1118U)
-#define DBSC_DBSCHQOS143			(DBSC_BASE + 0x111CU)
-#define DBSC_DBSCHQOS150			(DBSC_BASE + 0x1120U)
-#define DBSC_DBSCHQOS151			(DBSC_BASE + 0x1124U)
-#define DBSC_DBSCHQOS152			(DBSC_BASE + 0x1128U)
-#define DBSC_DBSCHQOS153			(DBSC_BASE + 0x112CU)
+#define	DBSC_BASE			(0xE6790000U)
+#define DBSC_DBSCHQOS00		(DBSC_BASE + 0x1030U)
+#define DBSC_DBSCHQOS01		(DBSC_BASE + 0x1034U)
+#define DBSC_DBSCHQOS02		(DBSC_BASE + 0x1038U)
+#define DBSC_DBSCHQOS03		(DBSC_BASE + 0x103CU)
+#define DBSC_DBSCHQOS40		(DBSC_BASE + 0x1070U)
+#define DBSC_DBSCHQOS41		(DBSC_BASE + 0x1074U)
+#define DBSC_DBSCHQOS42		(DBSC_BASE + 0x1078U)
+#define DBSC_DBSCHQOS43		(DBSC_BASE + 0x107CU)
+#define DBSC_DBSCHQOS90		(DBSC_BASE + 0x10C0U)
+#define DBSC_DBSCHQOS91		(DBSC_BASE + 0x10C4U)
+#define DBSC_DBSCHQOS92		(DBSC_BASE + 0x10C8U)
+#define DBSC_DBSCHQOS93		(DBSC_BASE + 0x10CCU)
+#define DBSC_DBSCHQOS120	(DBSC_BASE + 0x10F0U)
+#define DBSC_DBSCHQOS121	(DBSC_BASE + 0x10F4U)
+#define DBSC_DBSCHQOS122	(DBSC_BASE + 0x10F8U)
+#define DBSC_DBSCHQOS123	(DBSC_BASE + 0x10FCU)
+#define DBSC_DBSCHQOS130	(DBSC_BASE + 0x1100U)
+#define DBSC_DBSCHQOS131	(DBSC_BASE + 0x1104U)
+#define DBSC_DBSCHQOS132	(DBSC_BASE + 0x1108U)
+#define DBSC_DBSCHQOS133	(DBSC_BASE + 0x110CU)
+#define DBSC_DBSCHQOS140	(DBSC_BASE + 0x1110U)
+#define DBSC_DBSCHQOS141	(DBSC_BASE + 0x1114U)
+#define DBSC_DBSCHQOS142	(DBSC_BASE + 0x1118U)
+#define DBSC_DBSCHQOS143	(DBSC_BASE + 0x111CU)
+#define DBSC_DBSCHQOS150	(DBSC_BASE + 0x1120U)
+#define DBSC_DBSCHQOS151	(DBSC_BASE + 0x1124U)
+#define DBSC_DBSCHQOS152	(DBSC_BASE + 0x1128U)
+#define DBSC_DBSCHQOS153	(DBSC_BASE + 0x112CU)
diff --git a/plat/renesas/rcar/ddr/ddr_regdef.h b/plat/renesas/rcar/ddr/ddr_regdef.h
index 57187baecb..3cf80be72b 100644
--- a/plat/renesas/rcar/ddr/ddr_regdef.h
+++ b/plat/renesas/rcar/ddr/ddr_regdef.h
@@ -1,34 +1,3 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *   - Redistributions of source code must retain the above copyright notice,
- *     this list of conditions and the following disclaimer.
- *
- *   - Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *
- *   - Neither the name of Renesas nor the names of its contributors may be
- *     used to endorse or promote products derived from this software without
- *     specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
 #define _reg_PHY_DQ_DM_SWIZZLE0                            0x00000000U
 #define _reg_PHY_DQ_DM_SWIZZLE1                            0x00000001U
 #define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY                 0x00000002U
diff --git a/plat/renesas/rcar/ddr/init_dram_tbl_h3ver2.h b/plat/renesas/rcar/ddr/init_dram_tbl_h3ver2.h
index 616b46499c..82b8cbf2ed 100644
--- a/plat/renesas/rcar/ddr/init_dram_tbl_h3ver2.h
+++ b/plat/renesas/rcar/ddr/init_dram_tbl_h3ver2.h
@@ -66,7 +66,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2[DDR_PHY_SLICE_REGSET_NUM_H3VER
 /*040f*/	0x020100b0,
 /*0410*/	0x00030020,
 /*0411*/	0x00000000,
-/*0412*/	0x00000001,
+/*0412*/	0x00000000,
 /*0413*/	0x00000000,
 /*0414*/	0x00000000,
 /*0415*/	0x00000000,
@@ -372,7 +372,7 @@ static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = {
 /*023b*/	0x00000000,
 /*023c*/	0x00000000,
 /*023d*/	0x00000000,
-/*023e*/	0x04010100,
+/*023e*/	0x04010000,
 /*023f*/	0x00000404,
 /*0240*/	0x0101280a,
 /*0241*/	0x00000000,
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 389d0405b4..757a3d351e 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -285,11 +285,10 @@ ifeq (${RCAR_SYSTEM_SUSPEND},1)
   endif
 endif
 
-# Process LIFEC_DEBUG_TRACE_ENABLE flag
-ifndef LIFEC_DEBUG_TRACE_ENABLE
-LIFEC_DEBUG_TRACE_ENABLE := 0
+# Process RCAR_BL33_ARG0 flag
+ifdef RCAR_BL33_ARG0
+$(eval $(call add_define,RCAR_BL33_ARG0))
 endif
-$(eval $(call add_define,LIFEC_DEBUG_TRACE_ENABLE))
 
 include plat/renesas/rcar/ddr/ddr.mk
 include plat/renesas/rcar/qos/qos.mk
diff --git a/plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c b/plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
index d2220fa487..f735df20be 100644
--- a/plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+++ b/plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
@@ -35,7 +35,7 @@
 #include "../qos_reg.h"
 #include "qos_init_m3n_v10.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.03"
+#define	RCAR_QOS_VERSION		"rev.0.04"
 
 #define QOSCTRL_EARLYR			(QOS_BASE1 + 0x0060U)
 
diff --git a/plat/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h b/plat/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
index 129bca2650..0c9d0248f0 100644
--- a/plat/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
+++ b/plat/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
@@ -7,7 +7,7 @@ static uint64_t mstat_fix[]={
 	/* 0x0028, */ 0x0000000000000000U,
 	/* 0x0030, */ 0x001004320000FFFFU,
 	/* 0x0038, */ 0x001004320000FFFFU,
-	/* 0x0040, */ 0x001410740000FFFFU,
+	/* 0x0040, */ 0x00140C5D0000FFFFU,
 	/* 0x0048, */ 0x0000000000000000U,
 	/* 0x0050, */ 0x001404040000FFFFU,
 	/* 0x0058, */ 0x00140C940000FFFFU,
@@ -16,7 +16,7 @@ static uint64_t mstat_fix[]={
 	/* 0x0070, */ 0x001404040000FFFFU,
 	/* 0x0078, */ 0x0000000000000000U,
 	/* 0x0080, */ 0x0000000000000000U,
-	/* 0x0088, */ 0x001410740000FFFFU,
+	/* 0x0088, */ 0x0014041F0000FFFFU,
 	/* 0x0090, */ 0x0000000000000000U,
 	/* 0x0098, */ 0x0000000000000000U,
 	/* 0x00a0, */ 0x000C041D0000FFFFU,
@@ -41,7 +41,7 @@ static uint64_t mstat_fix[]={
 	/* 0x0138, */ 0x00100CA50000FFFFU,
 	/* 0x0140, */ 0x0000000000000000U,
 	/* 0x0148, */ 0x0000000000000000U,
-	/* 0x0150, */ 0x001010C70000FFFFU,
+	/* 0x0150, */ 0x001010C90000FFFFU,
 	/* 0x0158, */ 0x0000000000000000U,
 	/* 0x0160, */ 0x00100CA50000FFFFU,
 	/* 0x0168, */ 0x0000000000000000U,
@@ -49,7 +49,7 @@ static uint64_t mstat_fix[]={
 	/* 0x0178, */ 0x001008530000FFFFU,
 	/* 0x0180, */ 0x0000000000000000U,
 	/* 0x0188, */ 0x0000000000000000U,
-	/* 0x0190, */ 0x00102EB60000FFFFU,
+	/* 0x0190, */ 0x00101D9D0000FFFFU,
 	/* 0x0198, */ 0x0000000000000000U,
 	/* 0x01a0, */ 0x00100CA50000FFFFU,
 	/* 0x01a8, */ 0x0000000000000000U,
@@ -116,10 +116,10 @@ static uint64_t mstat_fix[]={
 	/* 0x0390, */ 0x0000000000000000U,
 };
 static uint64_t mstat_be[]={
-	/* 0x0000, */ 0x001206600BDFFC01U,
-	/* 0x0008, */ 0x001206600BDFFC01U,
-	/* 0x0010, */ 0x001206600BDFFC01U,
-	/* 0x0018, */ 0x001206600BDFFC01U,
+	/* 0x0000, */ 0x001203300BDFFC01U,
+	/* 0x0008, */ 0x001203300BDFFC01U,
+	/* 0x0010, */ 0x001203300BDFFC01U,
+	/* 0x0018, */ 0x001203300BDFFC01U,
 	/* 0x0020, */ 0x0000000000000000U,
 	/* 0x0028, */ 0x001200100BD03401U,
 	/* 0x0030, */ 0x0000000000000000U,
diff --git a/plat/renesas/rcar/qos/qos.mk b/plat/renesas/rcar/qos/qos.mk
index 8337917391..e29df09d7a 100644
--- a/plat/renesas/rcar/qos/qos.mk
+++ b/plat/renesas/rcar/qos/qos.mk
@@ -53,25 +53,31 @@ else
   ifeq (${RCAR_LSI},${RCAR_H3})
     ifeq (${LSI_CUT},10)
       BL2_SOURCES += plat/renesas/rcar/qos/H3/qos_init_h3_v10.c
-    endif
-    ifeq (${LSI_CUT},11)
+    else ifeq (${LSI_CUT},11)
       BL2_SOURCES += plat/renesas/rcar/qos/H3/qos_init_h3_v11.c
-    endif
-    ifeq (${LSI_CUT},20)
+    else ifeq (${LSI_CUT},20)
+      BL2_SOURCES += plat/renesas/rcar/qos/H3/qos_init_h3_v20.c
+    else
+#     LSI_CUT 20 or later
       BL2_SOURCES += plat/renesas/rcar/qos/H3/qos_init_h3_v20.c
     endif
   endif
   ifeq (${RCAR_LSI},${RCAR_M3})
     ifeq (${LSI_CUT},10)
      BL2_SOURCES += plat/renesas/rcar/qos/M3/qos_init_m3_v10.c
-    endif
-    ifeq (${LSI_CUT},11)
+    else ifeq (${LSI_CUT},11)
+     BL2_SOURCES += plat/renesas/rcar/qos/M3/qos_init_m3_v11.c
+    else
+#    LSI_CUT 11 or later
      BL2_SOURCES += plat/renesas/rcar/qos/M3/qos_init_m3_v11.c
     endif
   endif
   ifeq (${RCAR_LSI},${RCAR_M3N})
     ifeq (${LSI_CUT},10)
      BL2_SOURCES += plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+    else
+#    LSI_CUT 10 or later
+     BL2_SOURCES += plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
     endif
   endif
 endif
diff --git a/plat/renesas/rcar/qos/qos_init.c b/plat/renesas/rcar/qos/qos_init.c
index 573d04b367..ca0f31173c 100644
--- a/plat/renesas/rcar/qos/qos_init.c
+++ b/plat/renesas/rcar/qos/qos_init.c
@@ -94,10 +94,8 @@ void qos_init(void)
 			qos_init_h3_v11();
 			break;
 		case PRR_PRODUCT_20:
-			qos_init_h3_v20();
-			break;
 		default:
-			PRR_CUT_ERR(reg);
+			qos_init_h3_v20();
 			break;
 		}
  #else
@@ -111,10 +109,8 @@ void qos_init(void)
 			qos_init_m3_v10();
 			break;
 		case PRR_PRODUCT_20: /* M3 Cut 11 */
-			qos_init_m3_v11();
-			break;
 		default:
-			PRR_CUT_ERR(reg);
+			qos_init_m3_v11();
 			break;
 		}
  #else
@@ -125,10 +121,8 @@ void qos_init(void)
  #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
 		switch (reg & PRR_CUT_MASK) {
 		case PRR_PRODUCT_10:
-			qos_init_m3n_v10();
-			break;
 		default:
-			PRR_CUT_ERR(reg);
+			qos_init_m3n_v10();
 			break;
 		}
  #else
@@ -155,15 +149,13 @@ void qos_init(void)
 		PRR_PRODUCT_ERR(reg);
 	}
 	qos_init_h3_v11();
-  #elif RCAR_LSI_CUT == RCAR_CUT_20
-	/* H3 Cut 20 */
-	if ((PRR_PRODUCT_H3 | PRR_PRODUCT_20)
-			!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+  #else
+	/* H3 Cut 20 or later */
+	if ((PRR_PRODUCT_H3)
+			!= (reg & (PRR_PRODUCT_MASK))) {
 		PRR_PRODUCT_ERR(reg);
 	}
 	qos_init_h3_v20();
-  #else
-   #error "Don't have QoS initialize routine(H3)."
   #endif
  #elif RCAR_LSI == RCAR_M3	/* M3 */
   #if RCAR_LSI_CUT == RCAR_CUT_10
@@ -173,27 +165,21 @@ void qos_init(void)
 		PRR_PRODUCT_ERR(reg);
 	}
 	qos_init_m3_v10();
-  #elif RCAR_LSI_CUT == RCAR_CUT_11
-	/* M3 Cut 11 */
-	if ((PRR_PRODUCT_M3 | PRR_PRODUCT_20)
-			!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+  #else
+	/* M3 Cut 11 or later */
+	if ((PRR_PRODUCT_M3)
+			!= (reg & (PRR_PRODUCT_MASK))) {
 		PRR_PRODUCT_ERR(reg);
 	}
 	qos_init_m3_v11();
-  #else
-   #error "Don't have QoS initialize routine(M3)."
   #endif
  #elif RCAR_LSI == RCAR_M3N	/* M3N */
-  #if RCAR_LSI_CUT == RCAR_CUT_10
-	/* M3N Cut 10 */
-	if ((PRR_PRODUCT_M3N | PRR_PRODUCT_10)
-			!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+	/* M3N Cut 10 or later */
+	if ((PRR_PRODUCT_M3N)
+			!= (reg & (PRR_PRODUCT_MASK))) {
 		PRR_PRODUCT_ERR(reg);
 	}
 	qos_init_m3n_v10();
-  #else
-   #error "Don't have QoS initialize routine(M3N)."
-  #endif
  #else
   #error "Don't have QoS initialize routine(Unknown chip)."
  #endif