|
14 | 14 | +#include "rk3328-nanopi-r2s-u-boot.dtsi"
|
15 | 15 | --- /dev/null
|
16 | 16 | +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
|
17 |
| -@@ -0,0 +1,38 @@ |
| 17 | +@@ -0,0 +1,25 @@ |
18 | 18 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
19 | 19 | +#include "rk3328-nanopi-r2s.dts"
|
20 | 20 | +
|
|
23 | 23 | + compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
|
24 | 24 | +};
|
25 | 25 | +
|
26 |
| -+&lan_led { |
27 |
| -+ label = "orangepi-r1-plus:green:lan"; |
28 |
| -+}; |
29 |
| -+ |
30 | 26 | +&spi0 {
|
31 | 27 | + status = "okay";
|
32 | 28 | +
|
33 | 29 | + flash@0 {
|
34 | 30 | + compatible = "jedec,spi-nor";
|
35 | 31 | + reg = <0>;
|
36 |
| -+ spi-max-frequency = <10000000>; |
| 32 | ++ spi-max-frequency = <50000000>; |
37 | 33 | + };
|
38 | 34 | +};
|
39 | 35 | +
|
40 | 36 | +&sys_led {
|
41 | 37 | + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
42 |
| -+ label = "orangepi-r1-plus:red:sys"; |
43 | 38 | +};
|
44 | 39 | +
|
45 | 40 | +&sys_led_pin {
|
46 | 41 | + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
47 | 42 | +};
|
48 |
| -+ |
49 |
| -+&uart1 { |
50 |
| -+ status = "okay"; |
51 |
| -+}; |
52 |
| -+ |
53 |
| -+&wan_led { |
54 |
| -+ label = "orangepi-r1-plus:green:wan"; |
55 |
| -+}; |
56 |
| ---- a/board/rockchip/evb_rk3328/MAINTAINERS |
57 |
| -+++ b/board/rockchip/evb_rk3328/MAINTAINERS |
58 |
| -@@ -12,6 +12,13 @@ F: configs/nanopi-r2s-rk3328_defconfig |
59 |
| - F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi |
60 |
| - F: arch/arm/dts/rk3328-nanopi-r2s.dts |
61 |
| - |
62 |
| -+ORANGEPI-R1-PLUS-RK3328 |
63 |
| -+M: Shenzhen Xunlong Software CO.,Limited <[email protected]> |
64 |
| -+S: Maintained |
65 |
| -+F: configs/orangepi-r1-plus-rk3328_defconfig |
66 |
| -+F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi |
67 |
| -+F: arch/arm/dts/rk3328-orangepi-r1-plus.dts |
68 |
| -+ |
69 |
| - ROC-RK3328-CC |
70 |
| - M: Loic Devulder < [email protected]> |
71 |
| - M: Chen-Yu Tsai < [email protected]> |
72 | 43 | --- /dev/null
|
73 | 44 | +++ b/configs/orangepi-r1-plus-rk3328_defconfig
|
74 |
| -@@ -0,0 +1,100 @@ |
| 45 | +@@ -0,0 +1,104 @@ |
75 | 46 | +CONFIG_ARM=y
|
| 47 | ++CONFIG_SKIP_LOWLEVEL_INIT=y |
| 48 | ++CONFIG_COUNTER_FREQUENCY=24000000 |
76 | 49 | +CONFIG_ARCH_ROCKCHIP=y
|
77 | 50 | +CONFIG_SYS_TEXT_BASE=0x00200000
|
78 |
| -+CONFIG_SPL_GPIO_SUPPORT=y |
| 51 | ++CONFIG_SPL_GPIO=y |
| 52 | ++CONFIG_NR_DRAM_BANKS=1 |
79 | 53 | +CONFIG_ENV_OFFSET=0x3F8000
|
| 54 | ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" |
80 | 55 | +CONFIG_ROCKCHIP_RK3328=y
|
81 | 56 | +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
82 | 57 | +CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
83 | 58 | +CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
84 |
| -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 59 | ++CONFIG_SPL_DRIVERS_MISC=y |
85 | 60 | +CONFIG_SPL_STACK_R_ADDR=0x600000
|
86 |
| -+CONFIG_NR_DRAM_BANKS=1 |
87 |
| -+CONFIG_SYS_LOAD_ADDR=0x800800 |
88 | 61 | +CONFIG_DEBUG_UART_BASE=0xFF130000
|
89 | 62 | +CONFIG_DEBUG_UART_CLOCK=24000000
|
90 |
| -+CONFIG_SYSINFO=y |
| 63 | ++CONFIG_SYS_LOAD_ADDR=0x800800 |
91 | 64 | +CONFIG_DEBUG_UART=y
|
92 | 65 | +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
93 | 66 | +# CONFIG_ANDROID_BOOT_IMAGE is not set
|
94 | 67 | +CONFIG_FIT=y
|
95 | 68 | +CONFIG_FIT_VERBOSE=y
|
96 | 69 | +CONFIG_SPL_LOAD_FIT=y
|
97 | 70 | +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
|
98 |
| -+CONFIG_MISC_INIT_R=y |
99 | 71 | +# CONFIG_DISPLAY_CPUINFO is not set
|
100 | 72 | +CONFIG_DISPLAY_BOARDINFO_LATE=y
|
| 73 | ++CONFIG_MISC_INIT_R=y |
101 | 74 | +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
102 | 75 | +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
103 | 76 | +CONFIG_SPL_STACK_R=y
|
104 |
| -+CONFIG_SPL_I2C_SUPPORT=y |
105 |
| -+CONFIG_SPL_POWER_SUPPORT=y |
| 77 | ++CONFIG_SPL_I2C=y |
| 78 | ++CONFIG_SPL_POWER=y |
106 | 79 | +CONFIG_SPL_ATF=y
|
107 | 80 | +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
108 | 81 | +CONFIG_CMD_BOOTZ=y
|
|
113 | 86 | +CONFIG_CMD_TIME=y
|
114 | 87 | +CONFIG_SPL_OF_CONTROL=y
|
115 | 88 | +CONFIG_TPL_OF_CONTROL=y
|
116 |
| -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" |
117 | 89 | +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
118 | 90 | +CONFIG_TPL_OF_PLATDATA=y
|
119 | 91 | +CONFIG_ENV_IS_IN_MMC=y
|
120 | 92 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
| 93 | ++CONFIG_SYS_MMC_ENV_DEV=1 |
121 | 94 | +CONFIG_NET_RANDOM_ETHADDR=y
|
122 | 95 | +CONFIG_TPL_DM=y
|
123 | 96 | +CONFIG_REGMAP=y
|
|
142 | 115 | +CONFIG_SPL_PINCTRL=y
|
143 | 116 | +CONFIG_DM_PMIC=y
|
144 | 117 | +CONFIG_PMIC_RK8XX=y
|
| 118 | ++CONFIG_SPL_PMIC_RK8XX=y |
145 | 119 | +CONFIG_SPL_DM_REGULATOR=y
|
146 | 120 | +CONFIG_REGULATOR_PWM=y
|
147 | 121 | +CONFIG_DM_REGULATOR_FIXED=y
|
|
154 | 128 | +CONFIG_DM_RESET=y
|
155 | 129 | +CONFIG_BAUDRATE=1500000
|
156 | 130 | +CONFIG_DEBUG_UART_SHIFT=2
|
| 131 | ++CONFIG_SYSINFO=y |
157 | 132 | +CONFIG_SYSRESET=y
|
158 | 133 | +# CONFIG_TPL_SYSRESET is not set
|
159 | 134 | +CONFIG_USB=y
|
|
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