From a94492dac3f86ac8820d2cacb2892ad0fe0cb4a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Zasso?= Date: Mon, 20 Mar 2023 15:46:39 +0100 Subject: [PATCH] try patch --- .../v8/src/execution/arm64/simulator-arm64.cc | 5 ++++ .../src/trap-handler/trap-handler-simulator.h | 4 +++- deps/v8/test/cctest/test-assembler-arm64.cc | 24 +++++++++---------- 3 files changed, 20 insertions(+), 13 deletions(-) diff --git a/deps/v8/src/execution/arm64/simulator-arm64.cc b/deps/v8/src/execution/arm64/simulator-arm64.cc index 16cf4f3b84025e0..548cd3017bcbc18 100644 --- a/deps/v8/src/execution/arm64/simulator-arm64.cc +++ b/deps/v8/src/execution/arm64/simulator-arm64.cc @@ -34,6 +34,11 @@ #include "src/trap-handler/trap-handler-simulator.h" #endif // V8_ENABLE_WEBASSEMBLY +#if defined(_MSC_VER) +// define full memory barrier for msvc +#define __sync_synchronize _ReadWriteBarrier +#endif + namespace v8 { namespace internal { diff --git a/deps/v8/src/trap-handler/trap-handler-simulator.h b/deps/v8/src/trap-handler/trap-handler-simulator.h index 0ab80d202eee07f..627f8e8dad4fcba 100644 --- a/deps/v8/src/trap-handler/trap-handler-simulator.h +++ b/deps/v8/src/trap-handler/trap-handler-simulator.h @@ -34,8 +34,10 @@ uintptr_t ProbeMemory(uintptr_t address, uintptr_t pc) // "ProbeMemory", but we want something more expressive on stack traces. #if V8_OS_DARWIN asm("_v8_internal_simulator_ProbeMemory"); -#else +#elif !defined(_MSC_VER) asm("v8_internal_simulator_ProbeMemory"); +#else // MSVC + ; #endif } // namespace v8::internal::trap_handler diff --git a/deps/v8/test/cctest/test-assembler-arm64.cc b/deps/v8/test/cctest/test-assembler-arm64.cc index 05181d6542f01d8..68eeee6aa04a05a 100644 --- a/deps/v8/test/cctest/test-assembler-arm64.cc +++ b/deps/v8/test/cctest/test-assembler-arm64.cc @@ -14771,12 +14771,12 @@ static void AtomicMemoryWHelper(AtomicMemoryLoadSignature* load_funcs, AtomicMemoryStoreSignature* store_funcs, uint64_t arg1, uint64_t arg2, uint64_t expected, uint64_t result_mask) { - uint64_t data0[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; - uint64_t data1[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; - uint64_t data2[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; - uint64_t data3[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; - uint64_t data4[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; - uint64_t data5[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; + uint64_t data0[2] = {arg2, 0}; + uint64_t data1[2] = {arg2, 0}; + uint64_t data2[2] = {arg2, 0}; + uint64_t data3[2] = {arg2, 0}; + uint64_t data4[2] = {arg2, 0}; + uint64_t data5[2] = {arg2, 0}; SETUP(); SETUP_FEATURE(LSE); @@ -14838,12 +14838,12 @@ static void AtomicMemoryXHelper(AtomicMemoryLoadSignature* load_funcs, AtomicMemoryStoreSignature* store_funcs, uint64_t arg1, uint64_t arg2, uint64_t expected) { - uint64_t data0[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; - uint64_t data1[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; - uint64_t data2[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; - uint64_t data3[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; - uint64_t data4[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; - uint64_t data5[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0}; + uint64_t data0[2] = {arg2, 0}; + uint64_t data1[2] = {arg2, 0}; + uint64_t data2[2] = {arg2, 0}; + uint64_t data3[2] = {arg2, 0}; + uint64_t data4[2] = {arg2, 0}; + uint64_t data5[2] = {arg2, 0}; SETUP(); SETUP_FEATURE(LSE);