diff --git a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO_F091RC/nanoBooter/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO_F091RC/nanoBooter/mcuconf.h index 8fd5fde190..510d05857f 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO_F091RC/nanoBooter/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO_F091RC/nanoBooter/mcuconf.h @@ -1,18 +1,8 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// #ifndef _MCUCONF_H_ #define _MCUCONF_H_ @@ -241,4 +231,3 @@ #include "mcuconf_nf.h" #endif /* _MCUCONF_H_ */ - diff --git a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO_F091RC/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO_F091RC/nanoCLR/mcuconf.h index 39a76b8273..510d05857f 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO_F091RC/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO_F091RC/nanoCLR/mcuconf.h @@ -44,7 +44,6 @@ #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 #define STM32_PLLNODIV STM32_PLLNODIV_DIV2 -#define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI #define STM32_USART1SW STM32_USART1SW_PCLK @@ -59,25 +58,6 @@ #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 3 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 TRUE -#define STM32_DAC_USE_DAC1_CH2 TRUE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) - /* * EXT driver system settings. */ @@ -86,7 +66,6 @@ #define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 #define STM32_EXT_EXTI16_IRQ_PRIORITY 3 #define STM32_EXT_EXTI17_20_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3 /* * GPT driver system settings. @@ -94,12 +73,10 @@ #define STM32_GPT_USE_TIM1 FALSE #define STM32_GPT_USE_TIM2 FALSE #define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM14 FALSE #define STM32_GPT_TIM1_IRQ_PRIORITY 2 #define STM32_GPT_TIM2_IRQ_PRIORITY 2 #define STM32_GPT_TIM3_IRQ_PRIORITY 2 -#define STM32_GPT_TIM6_IRQ_PRIORITY 2 #define STM32_GPT_TIM14_IRQ_PRIORITY 2 /* @@ -138,25 +115,6 @@ #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI1 FALSE -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#define STM32_I2S_SPI1_IRQ_PRIORITY 2 -#define STM32_I2S_SPI2_IRQ_PRIORITY 2 -#define STM32_I2S_SPI1_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - /* * ICU driver system settings. */ @@ -183,8 +141,20 @@ */ #define STM32_SERIAL_USE_USART1 FALSE #define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE #define STM32_SERIAL_USART1_PRIORITY 3 #define STM32_SERIAL_USART2_PRIORITY 3 +#define STM32_SERIAL_USART3_PRIORITY 3 +#define STM32_SERIAL_UART4_PRIORITY 3 +#define STM32_SERIAL_UART5_PRIORITY 3 +#define STM32_SERIAL_USART6_PRIORITY 3 +#define STM32_SERIAL_UART7_PRIORITY 3 +#define STM32_SERIAL_UART8_PRIORITY 3 /* * SPI driver system settings. @@ -212,23 +182,46 @@ */ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE #define STM32_UART_USART1_IRQ_PRIORITY 3 #define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART3_IRQ_PRIORITY 3 +#define STM32_UART_UART4_IRQ_PRIORITY 3 +#define STM32_UART_UART5_IRQ_PRIORITY 3 +#define STM32_UART_USART6_IRQ_PRIORITY 3 +#define STM32_UART_UART7_IRQ_PRIORITY 3 +#define STM32_UART_UART8_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 FALSE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_LP_IRQ_PRIORITY 3 - /* * WDG driver system settings. */ @@ -238,4 +231,3 @@ #include "mcuconf_nf.h" #endif /* _MCUCONF_H_ */ -