-
Notifications
You must be signed in to change notification settings - Fork 25
/
Copy pathsnestang_primer25k.gprj
82 lines (82 loc) · 5.67 KB
/
snestang_primer25k.gprj
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW5A-25A" pn="GW5A-LV25MG121NC1/I0">gw5a25a-002</Device>
<FileList>
<File path="src/65C816/ALU.v" type="file.verilog" enable="1"/>
<File path="src/65C816/AddSubBCD.v" type="file.verilog" enable="1"/>
<File path="src/65C816/AddrGen.v" type="file.verilog" enable="1"/>
<File path="src/65C816/BCDAdder.v" type="file.verilog" enable="1"/>
<File path="src/65C816/P65C816.v" type="file.verilog" enable="1"/>
<File path="src/65C816/adder4.v" type="file.verilog" enable="1"/>
<File path="src/65C816/bit_adder.v" type="file.verilog" enable="1"/>
<File path="src/65C816/common.sv" type="file.verilog" enable="1"/>
<File path="src/65C816/mcode.sv" type="file.verilog" enable="1"/>
<File path="src/CEGen.v" type="file.verilog" enable="1"/>
<File path="src/chip/DSP/DSP_LHRomMap.v" type="file.verilog" enable="1"/>
<File path="src/chip/DSP/DSPn.v" type="file.verilog" enable="1"/>
<File path="src/chip/DSP/OBC1.v" type="file.verilog" enable="1"/>
<File path="src/chip/DSP/SRTC.v" type="file.verilog" enable="1"/>
<File path="src/chip/dsp/dsp_data_ram.v" type="file.verilog" enable="1"/>
<File path="src/controller_adapter.sv" type="file.verilog" enable="1"/>
<File path="src/controller_ds2.sv" type="file.verilog" enable="1"/>
<File path="src/controller_snes.v" type="file.verilog" enable="1"/>
<File path="src/cpu.v" type="file.verilog" enable="1"/>
<File path="src/dsp.v" type="file.verilog" enable="1"/>
<File path="src/dual_clk_fifo.v" type="file.verilog" enable="1"/>
<File path="src/dualshock_controller.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb_cgram.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb_hoam.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb_oam.v" type="file.verilog" enable="1"/>
<File path="src/hdmi2/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/audio_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/audio_sample_packet.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/hdmi.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/packet_assembler.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/packet_picker.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/serializer.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/source_product_description_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/tmds_channel.sv" type="file.verilog" enable="1"/>
<File path="src/iosys/gowin_dpb_menu.v" type="file.verilog" enable="1"/>
<File path="src/iosys/iosys.v" type="file.verilog" enable="1"/>
<File path="src/iosys/picorv32.v" type="file.verilog" enable="1"/>
<File path="src/iosys/simplespimaster.v" type="file.verilog" enable="1"/>
<File path="src/iosys/simpleuart.v" type="file.verilog" enable="1"/>
<File path="src/iosys/spi_master.v" type="file.verilog" enable="1"/>
<File path="src/iosys/spiflash.v" type="file.verilog" enable="1"/>
<File path="src/iosys/textdisp.v" type="file.verilog" enable="1"/>
<File path="src/main.v" type="file.verilog" enable="1"/>
<File path="src/mega138k/vram.v" type="file.verilog" enable="1"/>
<File path="src/mega138k/vram_spb.v" type="file.verilog" enable="1"/>
<File path="src/ppu.v" type="file.verilog" enable="1"/>
<File path="src/ppucgram.v" type="file.verilog" enable="1"/>
<File path="src/ppuhoam.v" type="file.verilog" enable="1"/>
<File path="src/ppuoam.v" type="file.verilog" enable="1"/>
<File path="src/primer25k/config.v" type="file.verilog" enable="1"/>
<File path="src/primer25k/gowin_pll_27.v" type="file.verilog" enable="1"/>
<File path="src/primer25k/gowin_pll_hdmi.v" type="file.verilog" enable="1"/>
<File path="src/primer25k/gowin_pll_snes.v" type="file.verilog" enable="1"/>
<File path="src/primer25k/sdram_cl2_3ch.v" type="file.verilog" enable="1"/>
<File path="src/smc_parser.v" type="file.verilog" enable="1"/>
<File path="src/smp.v" type="file.verilog" enable="1"/>
<File path="src/snes.v" type="file.verilog" enable="1"/>
<File path="src/snes2hdmi.v" type="file.verilog" enable="1"/>
<File path="src/snestang_top.v" type="file.verilog" enable="1"/>
<File path="src/spc700/_spc700_package.v" type="file.verilog" enable="1"/>
<File path="src/spc700/addrgen.v" type="file.verilog" enable="1"/>
<File path="src/spc700/addsub.v" type="file.verilog" enable="1"/>
<File path="src/spc700/alu.v" type="file.verilog" enable="1"/>
<File path="src/spc700/bcdadj.v" type="file.verilog" enable="1"/>
<File path="src/spc700/mcode.v" type="file.verilog" enable="1"/>
<File path="src/spc700/muldiv.v" type="file.verilog" enable="1"/>
<File path="src/spc700/spc700.v" type="file.verilog" enable="1"/>
<File path="src/swram.v" type="file.verilog" enable="1"/>
<File path="src/uart_tx_V2.v" type="file.verilog" enable="1"/>
<File path="src/primer25k/snestang.cst" type="file.cst" enable="1"/>
<File path="src/snestang.sdc" type="file.sdc" enable="1"/>
<File path="src/mega138k/snestang.gao" type="file.gao" enable="0"/>
</FileList>
</Project>