|
1 |
| -// |
2 |
| -// Copyright (c) 2014, ARM Limited. All rights reserved. |
3 |
| -// |
4 |
| -// This program and the accompanying materials are licensed and made available |
5 |
| -// under the terms and conditions of the BSD License which accompanies this |
6 |
| -// distribution. The full text of the license may be found at |
7 |
| -// http://opensource.org/licenses/bsd-license.php |
8 |
| -// |
9 |
| -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, |
10 |
| -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. |
11 |
| -// |
12 |
| -// |
13 |
| - |
14 |
| -#include <AsmMacroIoLibV8.h> |
15 |
| - |
16 |
| - AREA |.text|,ALIGN=3,CODE,READONLY |
17 |
| - |
18 |
| - EXPORT ArmGicV3GetControlSystemRegisterEnable |
19 |
| - EXPORT ArmGicV3SetControlSystemRegisterEnable |
20 |
| - EXPORT ArmGicV3SendNsG1Sgi // MU_CHANGE |
21 |
| - EXPORT ArmGicV3EnableInterruptInterface |
22 |
| - EXPORT ArmGicV3DisableInterruptInterface |
23 |
| - EXPORT ArmGicV3EndOfInterrupt |
24 |
| - EXPORT ArmGicV3AcknowledgeInterrupt |
25 |
| - EXPORT ArmGicV3SetPriorityMask |
26 |
| - EXPORT ArmGicV3SetBinaryPointer |
27 |
| - |
28 |
| -//UINT32 |
29 |
| -//EFIAPI |
30 |
| -//ArmGicV3GetControlSystemRegisterEnable ( |
31 |
| -// VOID |
32 |
| -// ); |
33 |
| -ArmGicV3GetControlSystemRegisterEnable PROC |
34 |
| - EL1_OR_EL2_OR_EL3(x1) |
35 |
| -1 |
36 |
| - mrs x0, ICC_SRE_EL1 |
37 |
| - b %f4 |
38 |
| -2 |
39 |
| - mrs x0, ICC_SRE_EL2 |
40 |
| - b %f4 |
41 |
| -3 |
42 |
| - mrs x0, ICC_SRE_EL3 |
43 |
| -4 |
44 |
| - ret |
45 |
| -ArmGicV3GetControlSystemRegisterEnable ENDP |
46 |
| - |
47 |
| -//VOID |
48 |
| -//EFIAPI |
49 |
| -//ArmGicV3SetControlSystemRegisterEnable ( |
50 |
| -// IN UINT32 ControlSystemRegisterEnable |
51 |
| -// ); |
52 |
| -ArmGicV3SetControlSystemRegisterEnable PROC |
53 |
| - EL1_OR_EL2_OR_EL3(x1) |
54 |
| -1 |
55 |
| - msr ICC_SRE_EL1, x0 |
56 |
| - b %f4 |
57 |
| -2 |
58 |
| - msr ICC_SRE_EL2, x0 |
59 |
| - b %f4 |
60 |
| -3 |
61 |
| - msr ICC_SRE_EL3, x0 |
62 |
| -4 |
63 |
| - isb sy |
64 |
| - ret |
65 |
| -ArmGicV3SetControlSystemRegisterEnable ENDP |
66 |
| - |
67 |
| -// MU_CHANGE Starts: Add ArmGicV3SendNsG1Sgi, to allow sending SGI from one core to other cores on GICv3 |
68 |
| -// VOID |
69 |
| -// ArmGicV3SendNsG1Sgi ( |
70 |
| -// IN UINT64 SgiVal |
71 |
| -// ); |
72 |
| -ArmGicV3SendNsG1Sgi PROC |
73 |
| - dsb ishst |
74 |
| - msr ICC_SGI1R_EL1, x0 |
75 |
| - isb |
76 |
| - ret |
77 |
| -ArmGicV3SendNsG1Sgi ENDP |
78 |
| -// MU_CHANGE Ends |
79 |
| - |
80 |
| -//VOID |
81 |
| -//ArmGicV3EnableInterruptInterface ( |
82 |
| -// VOID |
83 |
| -// ); |
84 |
| -ArmGicV3EnableInterruptInterface PROC |
85 |
| - mov x0, #1 |
86 |
| - msr ICC_IGRPEN1_EL1, x0 |
87 |
| - ret |
88 |
| -ArmGicV3EnableInterruptInterface ENDP |
89 |
| - |
90 |
| -//VOID |
91 |
| -//ArmGicV3DisableInterruptInterface ( |
92 |
| -// VOID |
93 |
| -// ); |
94 |
| -ArmGicV3DisableInterruptInterface PROC |
95 |
| - mov x0, #0 |
96 |
| - msr ICC_IGRPEN1_EL1, x0 |
97 |
| - ret |
98 |
| -ArmGicV3DisableInterruptInterface ENDP |
99 |
| - |
100 |
| -//VOID |
101 |
| -//ArmGicV3EndOfInterrupt ( |
102 |
| -// IN UINTN InterruptId |
103 |
| -// ); |
104 |
| -ArmGicV3EndOfInterrupt PROC |
105 |
| - msr ICC_EOIR1_EL1, x0 |
106 |
| - ret |
107 |
| -ArmGicV3EndOfInterrupt ENDP |
108 |
| - |
109 |
| -//UINTN |
110 |
| -//ArmGicV3AcknowledgeInterrupt ( |
111 |
| -// VOID |
112 |
| -// ); |
113 |
| -ArmGicV3AcknowledgeInterrupt PROC |
114 |
| - mrs x0, ICC_IAR1_EL1 |
115 |
| - ret |
116 |
| -ArmGicV3AcknowledgeInterrupt ENDP |
117 |
| - |
118 |
| -//VOID |
119 |
| -//ArmGicV3SetPriorityMask ( |
120 |
| -// IN UINTN Priority |
121 |
| -// ); |
122 |
| -ArmGicV3SetPriorityMask PROC |
123 |
| - msr ICC_PMR_EL1, x0 |
124 |
| - ret |
125 |
| -ArmGicV3SetPriorityMask ENDP |
126 |
| - |
127 |
| -//VOID |
128 |
| -//ArmGicV3SetBinaryPointer ( |
129 |
| -// IN UINTN BinaryPoint |
130 |
| -// ); |
131 |
| -ArmGicV3SetBinaryPointer PROC |
132 |
| - msr ICC_BPR1_EL1, x0 |
133 |
| - ret |
134 |
| -ArmGicV3SetBinaryPointer ENDP |
135 |
| - |
136 |
| - END |
| 1 | +// |
| 2 | +// Copyright (c) 2014, ARM Limited. All rights reserved. |
| 3 | +// |
| 4 | +// This program and the accompanying materials are licensed and made available |
| 5 | +// under the terms and conditions of the BSD License which accompanies this |
| 6 | +// distribution. The full text of the license may be found at |
| 7 | +// http://opensource.org/licenses/bsd-license.php |
| 8 | +// |
| 9 | +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, |
| 10 | +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. |
| 11 | +// |
| 12 | +// |
| 13 | +
|
| 14 | +#include <AsmMacroIoLibV8.h> |
| 15 | +
|
| 16 | + AREA |.text|,ALIGN=3,CODE,READONLY |
| 17 | +
|
| 18 | + EXPORT ArmGicV3GetControlSystemRegisterEnable |
| 19 | + EXPORT ArmGicV3SetControlSystemRegisterEnable |
| 20 | + EXPORT ArmGicV3SendNsG1Sgi // MU_CHANGE |
| 21 | + EXPORT ArmGicV3EnableInterruptInterface |
| 22 | + EXPORT ArmGicV3DisableInterruptInterface |
| 23 | + EXPORT ArmGicV3EndOfInterrupt |
| 24 | + EXPORT ArmGicV3AcknowledgeInterrupt |
| 25 | + EXPORT ArmGicV3SetPriorityMask |
| 26 | + EXPORT ArmGicV3SetBinaryPointer |
| 27 | +
|
| 28 | +//UINT32 |
| 29 | +//EFIAPI |
| 30 | +//ArmGicV3GetControlSystemRegisterEnable ( |
| 31 | +// VOID |
| 32 | +// ); |
| 33 | +ArmGicV3GetControlSystemRegisterEnable PROC |
| 34 | + EL1_OR_EL2_OR_EL3(x1) |
| 35 | +1 |
| 36 | + mrs x0, ICC_SRE_EL1 |
| 37 | + b %f4 |
| 38 | +2 |
| 39 | + mrs x0, ICC_SRE_EL2 |
| 40 | + b %f4 |
| 41 | +3 |
| 42 | + mrs x0, ICC_SRE_EL3 |
| 43 | +4 |
| 44 | + ret |
| 45 | +ArmGicV3GetControlSystemRegisterEnable ENDP |
| 46 | +
|
| 47 | +//VOID |
| 48 | +//EFIAPI |
| 49 | +//ArmGicV3SetControlSystemRegisterEnable ( |
| 50 | +// IN UINT32 ControlSystemRegisterEnable |
| 51 | +// ); |
| 52 | +ArmGicV3SetControlSystemRegisterEnable PROC |
| 53 | + EL1_OR_EL2_OR_EL3(x1) |
| 54 | +1 |
| 55 | + msr ICC_SRE_EL1, x0 |
| 56 | + b %f4 |
| 57 | +2 |
| 58 | + msr ICC_SRE_EL2, x0 |
| 59 | + b %f4 |
| 60 | +3 |
| 61 | + msr ICC_SRE_EL3, x0 |
| 62 | +4 |
| 63 | + isb sy |
| 64 | + ret |
| 65 | +ArmGicV3SetControlSystemRegisterEnable ENDP |
| 66 | +
|
| 67 | +// MU_CHANGE Starts: Add ArmGicV3SendNsG1Sgi, to allow sending SGI from one core to other cores on GICv3 |
| 68 | +// VOID |
| 69 | +// ArmGicV3SendNsG1Sgi ( |
| 70 | +// IN UINT64 SgiVal |
| 71 | +// ); |
| 72 | +ArmGicV3SendNsG1Sgi PROC |
| 73 | + dsb ishst |
| 74 | + msr ICC_SGI1R_EL1, x0 |
| 75 | + isb |
| 76 | + ret |
| 77 | +ArmGicV3SendNsG1Sgi ENDP |
| 78 | +// MU_CHANGE Ends |
| 79 | +
|
| 80 | +//VOID |
| 81 | +//ArmGicV3EnableInterruptInterface ( |
| 82 | +// VOID |
| 83 | +// ); |
| 84 | +ArmGicV3EnableInterruptInterface PROC |
| 85 | + mov x0, #1 |
| 86 | + msr ICC_IGRPEN1_EL1, x0 |
| 87 | + ret |
| 88 | +ArmGicV3EnableInterruptInterface ENDP |
| 89 | +
|
| 90 | +//VOID |
| 91 | +//ArmGicV3DisableInterruptInterface ( |
| 92 | +// VOID |
| 93 | +// ); |
| 94 | +ArmGicV3DisableInterruptInterface PROC |
| 95 | + mov x0, #0 |
| 96 | + msr ICC_IGRPEN1_EL1, x0 |
| 97 | + ret |
| 98 | +ArmGicV3DisableInterruptInterface ENDP |
| 99 | +
|
| 100 | +//VOID |
| 101 | +//ArmGicV3EndOfInterrupt ( |
| 102 | +// IN UINTN InterruptId |
| 103 | +// ); |
| 104 | +ArmGicV3EndOfInterrupt PROC |
| 105 | + msr ICC_EOIR1_EL1, x0 |
| 106 | + ret |
| 107 | +ArmGicV3EndOfInterrupt ENDP |
| 108 | +
|
| 109 | +//UINTN |
| 110 | +//ArmGicV3AcknowledgeInterrupt ( |
| 111 | +// VOID |
| 112 | +// ); |
| 113 | +ArmGicV3AcknowledgeInterrupt PROC |
| 114 | + mrs x0, ICC_IAR1_EL1 |
| 115 | + ret |
| 116 | +ArmGicV3AcknowledgeInterrupt ENDP |
| 117 | +
|
| 118 | +//VOID |
| 119 | +//ArmGicV3SetPriorityMask ( |
| 120 | +// IN UINTN Priority |
| 121 | +// ); |
| 122 | +ArmGicV3SetPriorityMask PROC |
| 123 | + msr ICC_PMR_EL1, x0 |
| 124 | + ret |
| 125 | +ArmGicV3SetPriorityMask ENDP |
| 126 | +
|
| 127 | +//VOID |
| 128 | +//ArmGicV3SetBinaryPointer ( |
| 129 | +// IN UINTN BinaryPoint |
| 130 | +// ); |
| 131 | +ArmGicV3SetBinaryPointer PROC |
| 132 | + msr ICC_BPR1_EL1, x0 |
| 133 | + ret |
| 134 | +ArmGicV3SetBinaryPointer ENDP |
| 135 | +
|
| 136 | + END |
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