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kuqin12apop5
kuqin12
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apop5
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ArmPlatformPkg: CodeQL Fixes.
Makes changes to comply with alerts raised by CodeQL. The issues here fall into the following category: 1. comparison-with-wider-type
1 parent 7d946d7 commit aded147

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7 files changed

+27
-27
lines changed

7 files changed

+27
-27
lines changed

‎ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c

+16-16
Original file line numberDiff line numberDiff line change
@@ -140,10 +140,10 @@ VideoCopyHorizontalOverlap (
140140
UINT16 *SourcePixel16bit;
141141
UINT16 *DestinationPixel16bit;
142142

143-
UINT32 SourcePixelY;
144-
UINT32 DestinationPixelY;
145-
UINTN SizeIn32Bits;
146-
UINTN SizeIn16Bits;
143+
UINTN SourcePixelY; // MU_CHANGE - CodeQL Change
144+
UINTN DestinationPixelY; // MU_CHANGE - CodeQL Change
145+
UINTN SizeIn32Bits;
146+
UINTN SizeIn16Bits;
147147

148148
Status = EFI_SUCCESS;
149149

@@ -271,8 +271,8 @@ BltVideoFill (
271271
VOID *DestinationAddr;
272272
UINT16 *DestinationPixel16bit;
273273
UINT16 Pixel16bit;
274-
UINT32 DestinationPixelX;
275-
UINT32 DestinationLine;
274+
UINTN DestinationPixelX; // MU_CHANGE - CodeQL Change
275+
UINTN DestinationLine; // MU_CHANGE - CodeQL Change
276276
UINTN WidthInBytes;
277277

278278
Status = EFI_SUCCESS;
@@ -420,11 +420,11 @@ BltVideoToBltBuffer (
420420
VOID *DestinationAddr;
421421
UINT16 *SourcePixel16bit;
422422
UINT16 Pixel16bit;
423-
UINT32 SourcePixelX;
424-
UINT32 SourceLine;
425-
UINT32 DestinationPixelX;
426-
UINT32 DestinationLine;
427-
UINT32 BltBufferHorizontalResolution;
423+
UINTN SourcePixelX; // MU_CHANGE - CodeQL Change
424+
UINTN SourceLine; // MU_CHANGE - CodeQL Change
425+
UINTN DestinationPixelX; // MU_CHANGE - CodeQL Change
426+
UINTN DestinationLine; // MU_CHANGE - CodeQL Change
427+
UINTN BltBufferHorizontalResolution; // MU_CHANGE - CodeQL Change
428428
UINTN WidthInBytes;
429429

430430
Status = EFI_SUCCESS;
@@ -583,11 +583,11 @@ BltBufferToVideo (
583583
VOID *SourceAddr;
584584
VOID *DestinationAddr;
585585
UINT16 *DestinationPixel16bit;
586-
UINT32 SourcePixelX;
587-
UINT32 SourceLine;
588-
UINT32 DestinationPixelX;
589-
UINT32 DestinationLine;
590-
UINT32 BltBufferHorizontalResolution;
586+
UINTN SourcePixelX; // MU_CHANGE - CodeQL Change
587+
UINTN SourceLine; // MU_CHANGE - CodeQL Change
588+
UINTN DestinationPixelX; // MU_CHANGE - CodeQL Change
589+
UINTN DestinationLine; // MU_CHANGE - CodeQL Change
590+
UINTN BltBufferHorizontalResolution; // MU_CHANGE - CodeQL Change
591591
UINTN WidthInBytes;
592592

593593
Status = EFI_SUCCESS;

‎ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ PL061SetPins (
100100
IN UINTN Value
101101
)
102102
{
103-
MmioWrite8 (PL061EffectiveAddress (Address, Mask), Value);
103+
MmioWrite8 (PL061EffectiveAddress (Address, Mask), (UINT8)Value); // MU_CHANGE - CodeQL Change
104104
}
105105

106106
/**
@@ -236,14 +236,14 @@ Set (
236236

237237
case GPIO_MODE_OUTPUT_0:
238238
// Set the corresponding direction bit to HIGH for output
239-
MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK (Offset));
239+
MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, (UINT8)GPIO_PIN_MASK (Offset)); // MU_CHANGE - CodeQL Change
240240
// Set the corresponding data bit to LOW for 0
241241
PL061SetPins (RegisterBase, GPIO_PIN_MASK (Offset), 0);
242242
break;
243243

244244
case GPIO_MODE_OUTPUT_1:
245245
// Set the corresponding direction bit to HIGH for output
246-
MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK (Offset));
246+
MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, (UINT8)GPIO_PIN_MASK (Offset)); // MU_CHANGE - CodeQL Change
247247
// Set the corresponding data bit to HIGH for 1
248248
PL061SetPins (RegisterBase, GPIO_PIN_MASK (Offset), 0xff);
249249
break;

‎ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,6 @@
3737
#define PL061_GPIO_PINS 8
3838

3939
// All bits low except one bit high, native bit length
40-
#define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
40+
#define GPIO_PIN_MASK(Pin) (LShiftU64(1UL, Pin)) // MU_CHANGE - CodeQL
4141

4242
#endif // __PL061_GPIO_H__

‎ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
STATIC EFI_EVENT mEfiExitBootServicesEvent;
2525
STATIC EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterrupt;
2626
STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;
27-
STATIC UINT32 mTimerPeriod;
27+
STATIC UINT64 mTimerPeriod; // MU_CHANGE - CodeQL Change
2828

2929
/**
3030
Make sure the SP805 registers are unlocked for writing.
@@ -101,7 +101,7 @@ SP805Stop (
101101
{
102102
// Disable interrupts
103103
if ((MmioRead32 (SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) != 0) {
104-
MmioAnd32 (SP805_WDOG_CONTROL_REG, ~SP805_WDOG_CTRL_INTEN);
104+
MmioAnd32 (SP805_WDOG_CONTROL_REG, (UINT32) ~SP805_WDOG_CTRL_INTEN); // MU_CHANGE - CodeQL Change
105105
}
106106
}
107107

‎ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@ LcdSetMode (
117117
}
118118

119119
// Disable the CLCD_LcdEn bit
120-
MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);
120+
MmioAnd32 (PL111_REG_LCD_CONTROL, (UINT32) ~PL111_CTRL_LCD_EN); // MU_CHANGE - CodeQL Change
121121

122122
// Set Timings
123123
MmioWrite32 (
@@ -167,5 +167,5 @@ LcdShutdown (
167167
)
168168
{
169169
// Disable the controller
170-
MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);
170+
MmioAnd32 (PL111_REG_LCD_CONTROL, (UINT32) ~PL111_CTRL_LCD_EN); // MU_CHANGE - CodeQL Change
171171
}

‎ArmPlatformPkg/PrePeiCore/MainMPCore.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ SecondaryMain (
7979
ASSERT (Index != ArmCoreCount);
8080

8181
// Clear Secondary cores MailBox
82-
MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
82+
MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, (UINT32)ArmCoreInfoTable[Index].MailboxClearValue); // MU_CHANGE - CodeQL Change
8383

8484
do {
8585
ArmCallWFI ();
@@ -124,7 +124,7 @@ PrimaryMain (
124124
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
125125
if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
126126
// Sending SGI to all the Secondary CPU interfaces
127-
ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
127+
ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), (UINT8)ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, (UINT8)0x0E, (UINT8)PcdGet32 (PcdGicSgiIntId));
128128
}
129129

130130
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at

‎ArmPlatformPkg/PrePi/MainMPCore.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ PrimaryMain (
2525
// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization
2626
if (!FixedPcdGet32 (PcdSendSgiToBringUpSecondaryCores)) {
2727
// Sending SGI to all the Secondary CPU interfaces
28-
ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
28+
ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, (UINT8)PcdGet32 (PcdGicSgiIntId)); // MU_CHANGE - CodeQL Change
2929
}
3030

3131
PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);

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