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kkennettmakubackichris-oo
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Add changes required for arm64 vs tools to work
First batch of changes to permit VS2017 ARM64 tools to build required elements. Co-authored-by: Michael Kubacki <[email protected]> Co-authored-by: Chris Oo <[email protected]>
1 parent ed6c448 commit 41c7073

32 files changed

+2413
-41
lines changed

‎ArmPkg/Drivers/ArmGic/ArmGicLib.c

+2-4
Original file line numberDiff line numberDiff line change
@@ -148,10 +148,8 @@ ArmGicSendSgiTo (
148148
{
149149
MmioWrite32 (
150150
GicDistributorBase + ARM_GIC_ICDSGIR,
151-
((TargetListFilter & 0x3) << 24) |
152-
((CPUTargetList & 0xFF) << 16) |
153-
(SgiId & 0xF)
154-
);
151+
(UINT32)(((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | (SgiId & 0xF))
152+
); // MU_CHANGE
155153
}
156154

157155
/*

‎ArmPkg/Drivers/ArmGic/ArmGicLib.inf

+2-1
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,8 @@
2424
GicV3/Arm/ArmGicV3.S | GCC
2525

2626
[Sources.AARCH64]
27-
GicV3/AArch64/ArmGicV3.S
27+
GicV3/AArch64/ArmGicV3.S | GCC # MU_CHANGE - ARM64 VS change
28+
GicV3/AArch64/ArmGicV3.masm | MSFT # MU_CHANGE - ARM64 VS change
2829

2930
[LibraryClasses]
3031
ArmLib

‎ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,7 @@ GicV2IrqInterruptHandler (
165165
UINTN GicInterrupt;
166166
HARDWARE_INTERRUPT_HANDLER InterruptHandler;
167167

168-
GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
168+
GicInterrupt = (UINT32)ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase); // MU_CHANGE - ARM64 VS change
169169

170170
// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the
171171
// number of interrupt (ie: Spurious interrupt).
@@ -359,7 +359,7 @@ GicV2ExitBootServicesEvent (
359359

360360
// Acknowledge all pending interrupts
361361
do {
362-
GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
362+
GicInterrupt = (UINT32)ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase); // MU_CHANGE - ARM64 VS change
363363

364364
if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) {
365365
GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);

‎ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.masm

+122
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
//
2+
// Copyright (c) 2014, ARM Limited. All rights reserved.
3+
//
4+
// This program and the accompanying materials are licensed and made available
5+
// under the terms and conditions of the BSD License which accompanies this
6+
// distribution. The full text of the license may be found at
7+
// http://opensource.org/licenses/bsd-license.php
8+
//
9+
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10+
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11+
//
12+
//
13+
14+
#include <AsmMacroIoLibV8.h>
15+
16+
AREA |.text|,ALIGN=3,CODE,READONLY
17+
18+
EXPORT ArmGicV3GetControlSystemRegisterEnable
19+
EXPORT ArmGicV3SetControlSystemRegisterEnable
20+
EXPORT ArmGicV3EnableInterruptInterface
21+
EXPORT ArmGicV3DisableInterruptInterface
22+
EXPORT ArmGicV3EndOfInterrupt
23+
EXPORT ArmGicV3AcknowledgeInterrupt
24+
EXPORT ArmGicV3SetPriorityMask
25+
EXPORT ArmGicV3SetBinaryPointer
26+
27+
//UINT32
28+
//EFIAPI
29+
//ArmGicV3GetControlSystemRegisterEnable (
30+
// VOID
31+
// );
32+
ArmGicV3GetControlSystemRegisterEnable PROC
33+
EL1_OR_EL2_OR_EL3(x1)
34+
1
35+
mrs x0, ICC_SRE_EL1
36+
b %f4
37+
2
38+
mrs x0, ICC_SRE_EL2
39+
b %f4
40+
3
41+
mrs x0, ICC_SRE_EL3
42+
4
43+
ret
44+
ArmGicV3GetControlSystemRegisterEnable ENDP
45+
46+
//VOID
47+
//EFIAPI
48+
//ArmGicV3SetControlSystemRegisterEnable (
49+
// IN UINT32 ControlSystemRegisterEnable
50+
// );
51+
ArmGicV3SetControlSystemRegisterEnable PROC
52+
EL1_OR_EL2_OR_EL3(x1)
53+
1
54+
msr ICC_SRE_EL1, x0
55+
b %f4
56+
2
57+
msr ICC_SRE_EL2, x0
58+
b %f4
59+
3
60+
msr ICC_SRE_EL3, x0
61+
4
62+
isb sy
63+
ret
64+
ArmGicV3SetControlSystemRegisterEnable ENDP
65+
66+
//VOID
67+
//ArmGicV3EnableInterruptInterface (
68+
// VOID
69+
// );
70+
ArmGicV3EnableInterruptInterface PROC
71+
mov x0, #1
72+
msr ICC_IGRPEN1_EL1, x0
73+
ret
74+
ArmGicV3EnableInterruptInterface ENDP
75+
76+
//VOID
77+
//ArmGicV3DisableInterruptInterface (
78+
// VOID
79+
// );
80+
ArmGicV3DisableInterruptInterface PROC
81+
mov x0, #0
82+
msr ICC_IGRPEN1_EL1, x0
83+
ret
84+
ArmGicV3DisableInterruptInterface ENDP
85+
86+
//VOID
87+
//ArmGicV3EndOfInterrupt (
88+
// IN UINTN InterruptId
89+
// );
90+
ArmGicV3EndOfInterrupt PROC
91+
msr ICC_EOIR1_EL1, x0
92+
ret
93+
ArmGicV3EndOfInterrupt ENDP
94+
95+
//UINTN
96+
//ArmGicV3AcknowledgeInterrupt (
97+
// VOID
98+
// );
99+
ArmGicV3AcknowledgeInterrupt PROC
100+
mrs x0, ICC_IAR1_EL1
101+
ret
102+
ArmGicV3AcknowledgeInterrupt ENDP
103+
104+
//VOID
105+
//ArmGicV3SetPriorityMask (
106+
// IN UINTN Priority
107+
// );
108+
ArmGicV3SetPriorityMask PROC
109+
msr ICC_PMR_EL1, x0
110+
ret
111+
ArmGicV3SetPriorityMask ENDP
112+
113+
//VOID
114+
//ArmGicV3SetBinaryPointer (
115+
// IN UINTN BinaryPoint
116+
// );
117+
ArmGicV3SetBinaryPointer PROC
118+
msr ICC_BPR1_EL1, x0
119+
ret
120+
ArmGicV3SetBinaryPointer ENDP
121+
122+
END

‎ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -423,7 +423,7 @@ GicV3DxeInitialize (
423423
for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
424424
MmioWrite32 (
425425
mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),
426-
CpuTarget
426+
(UINT32)CpuTarget // MU_CHANGE - ARM64 VS change
427427
);
428428
}
429429
}
@@ -460,7 +460,7 @@ GicV3DxeInitialize (
460460
for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
461461
MmioWrite64 (
462462
mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
463-
CpuTarget
463+
(UINT32)CpuTarget // MU_CHANGE - ARM64 VS change
464464
);
465465
}
466466
}

‎ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c

+3-2
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
2424
2525
@param T0SZ The T0SZ value to be parsed.
2626
@param RootTableLevel The level of the root table.
27-
@param RootTableEntryCount The number of entries in the root table.
27+
@param RootTableEntryCount T
28+
he number of entries in the root table.
2829
**/
2930
STATIC
3031
VOID
@@ -314,7 +315,7 @@ SyncCacheConfig (
314315
GetRootTranslationTableInfo (T0SZ, &TableLevel, &TableCount);
315316

316317
// First Attribute of the Page Tables
317-
PageAttribute = GetFirstPageAttribute (FirstLevelTableAddress, TableLevel);
318+
PageAttribute = (UINT32)GetFirstPageAttribute (FirstLevelTableAddress, TableLevel); // MU_CHANGE - ARM64 VS change
318319

319320
// We scan from the start of the memory map (ie: at the address 0x0)
320321
BaseAddressGcdRegion = 0x0;

‎ArmPkg/Drivers/CpuDxe/CpuDxe.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -226,7 +226,7 @@ InitializeDma (
226226
IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol
227227
)
228228
{
229-
CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();
229+
CpuArchProtocol->DmaBufferAlignment = (UINT32)ArmCacheWritebackGranule (); // MU_CHANGE - ARM64 VS change
230230
}
231231

232232
/**

‎ArmPkg/Drivers/TimerDxe/TimerDxe.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ TimerDriverSetTimerPeriod (
143143
// mTimerTicks = TimerPeriod in 1ms unit x Frequency.10^-3
144144
// = TimerPeriod.10^-4 x Frequency.10^-3
145145
// = (TimerPeriod x Frequency) x 10^-7
146-
TimerTicks = MultU64x32 (TimerPeriod, ArmGenericTimerGetTimerFreq ());
146+
TimerTicks = MultU64x32 (TimerPeriod, (UINT32)ArmGenericTimerGetTimerFreq ()); // MU_CHANGE - ARM64 VS change
147147
TimerTicks = DivU64x32 (TimerTicks, 10000000U);
148148

149149
// Raise TPL to update the mTimerTicks and mTimerPeriod to ensure these values

‎ArmPkg/Include/AsmMacroIoLibV8.h

+84-7
Original file line numberDiff line numberDiff line change
@@ -12,46 +12,121 @@
1212
#ifndef ASM_MACRO_IO_LIBV8_H_
1313
#define ASM_MACRO_IO_LIBV8_H_
1414

15+
// MU_CHANGE [BEGIN] - ARM64 VS change
16+
// This is gross but GCC doesn't follow the C++ spec and is using a '#' in macro definitions.
17+
//
18+
#define CATSTR2(x, y) x##y
19+
#define CATSTR(x, y) CATSTR2(x,y)
20+
#define NUM(x) CATSTR(HASH,x)
21+
#define HASH #
22+
// MU_CHANGE [END] - ARM64 VS change
23+
1524
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
1625
// This only selects between EL1 and EL2, else we die.
1726
// Provide the Macro with a safe temp xreg to use.
27+
#if !defined (_MSC_VER) // MU_CHANGE - ARM64 VS change
1828
#define EL1_OR_EL2(SAFE_XREG) \
1929
mrs SAFE_XREG, CurrentEL ;\
2030
cmp SAFE_XREG, #0x8 ;\
2131
b.gt . ;\
2232
b.eq 2f ;\
2333
cbnz SAFE_XREG, 1f ;\
2434
b . ;// We should never get here
25-
35+
// MU_CHANGE [BEGIN] - ARM64 VS change
36+
#else
37+
#define EL1_OR_EL2(SAFE_XREG) \
38+
mrs SAFE_XREG, CurrentEL __CR__\
39+
cmp SAFE_XREG, NUM(0x8) __CR__\
40+
6
41+
bgt %b6 __CR__ \
42+
beq %f2 __CR__ \
43+
cbnz SAFE_XREG, NUM (0x4) __CR__ \
44+
5 __CR__ \
45+
bne %b5 // We should never get here
46+
#endif
47+
// EL1 code starts here
48+
// MU_CHANGE [END] - ARM64 VS change
2649
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
2750
// This only selects between EL1 and EL2 and EL3, else we die.
2851
// Provide the Macro with a safe temp xreg to use.
52+
#if !defined (_MSC_VER) // MU_CHANGE - ARM64 VS change
2953
#define EL1_OR_EL2_OR_EL3(SAFE_XREG) \
3054
mrs SAFE_XREG, CurrentEL ;\
3155
cmp SAFE_XREG, #0x8 ;\
3256
b.gt 3f ;\
3357
b.eq 2f ;\
3458
cbnz SAFE_XREG, 1f ;\
3559
b . ;// We should never get here
60+
// MU_CHANGE [BEGIN] - ARM64 VS change
61+
#else
62+
#define EL1_OR_EL2_OR_EL3(SAFE_XREG) \
63+
mrs SAFE_XREG, CurrentEL __CR__\
64+
cmp SAFE_XREG, NUM(0x8) __CR__\
65+
bgt %f3 __CR__\
66+
beq %f2 __CR__\
67+
cbnz SAFE_XREG, %f1 __CR__\
68+
5 __CR__\
69+
bne %b5 // We should never get here
70+
#endif
71+
// EL1 code starts here
72+
73+
#if defined (_MSC_VER)
74+
75+
// MU_CHANGE - add
76+
#define LoadConstantToReg(Data, Reg) \
77+
ldr Reg, =Data
78+
79+
#elif defined (__clang__)
80+
81+
// load x0 with _Data
82+
#define LoadConstant(_Data) \
83+
ldr x0, 1f ; \
84+
b 2f ; \
85+
.align(8) ; \
86+
1: \
87+
.8byte (_Data) ; \
88+
2:
3689

37-
#ifndef __clang__ // MU_CHANGE
90+
// load _Reg with _Data
91+
#define LoadConstantToReg(_Data, _Reg) \
92+
ldr _Reg, 1f ; \
93+
b 2f ; \
94+
.align(8) ; \
95+
1: \
96+
.8byte (_Data) ; \
97+
2:
98+
99+
#elif defined (__GNUC__)
100+
101+
#define LoadConstant(Data) \
102+
ldr x0, =Data
103+
104+
#define LoadConstantToReg(Data, Reg) \
105+
ldr Reg, =Data
106+
107+
#endif // __GNUC__
108+
109+
#if !defined (_MSC_VER)
110+
// MU_CHANGE [END] - ARM64 VS change
111+
112+
#ifndef __clang__ // MU_CHANGE
38113
#define _ASM_FUNC(Name, Section) \
39114
.global Name ; \
40115
.section #Section, "ax" ; \
41116
.type Name, %function ; \
42117
Name: ; \
43118
AARCH64_BTI(c)
44119
// MU_CHANGE Starts: CLANGPDB support
45-
#else
120+
#else
46121
#define _ASM_FUNC(Name, Section) \
47122
.global Name ; \
48123
.section #Section, "ax" ; \
49124
Name: ; \
50125
AARCH64_BTI(c)
51-
#endif
126+
#endif
52127
// MU_CHANGE Ends
53128

54-
#ifndef __clang__ // MU_CHANGE
129+
#ifndef __clang__ // MU_CHANGE
55130
#define _ASM_FUNC_ALIGN(Name, Section, Align) \
56131
.global Name ; \
57132
.section #Section, "ax" ; \
@@ -60,14 +135,14 @@
60135
Name: ; \
61136
AARCH64_BTI(c)
62137
// MU_CHANGE Starts: CLANGPDB support
63-
#else
138+
#else
64139
#define _ASM_FUNC_ALIGN(Name, Section, Align) \
65140
.global Name ; \
66141
.section #Section, "ax" ; \
67142
.balign Align ; \
68143
Name: ; \
69144
AARCH64_BTI(c)
70-
#endif
145+
#endif
71146
// MU_CHANGE Ends
72147

73148
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
@@ -85,4 +160,6 @@
85160
movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \
86161
movk Reg, (Val) & 0xffff
87162

163+
#endif // MU_CHANGE - ARM64 VS change
164+
88165
#endif // ASM_MACRO_IO_LIBV8_H_

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