Why does 32-bit ARM use __ldrexd instead of __iso_volatile_load64?

[AlexGuteniev]

Why does 32-bit ARM use __ldrexd instead of __iso_volatile_load64?

Note that ldrexd is generally useful with strexd, however strexd is not even exposed as intrinsic, so __ldrexd intrinsic is probably exposed specifically for this usage.

(This does not block something, but this is the only two lines of <atomic> I don't understand fully)

Occurrences:

STL/stl/inc/atomic

Lines 827 to 838 in c10ae01

	_NODISCARD _Ty load() const noexcept { // load with sequential consistency
	const auto _Mem = _Atomic_address_as<long long>(_Storage);
	long long _As_bytes;
	#ifdef _M_ARM
	_As_bytes = __ldrexd(_Mem);
	_Memory_barrier();
	#else
	_As_bytes = __iso_volatile_load64(_Mem);
	_Compiler_or_memory_barrier();
	#endif
	return reinterpret_cast<_Ty&>(_As_bytes);
	}

STL/stl/inc/atomic

Lines 840 to 849 in c10ae01

	_NODISCARD _Ty load(const memory_order _Order) const noexcept { // load with given memory order
	const auto _Mem = _Atomic_address_as<long long>(_Storage);
	#ifdef _M_ARM
	long long _As_bytes = __ldrexd(_Mem);
	#else
	long long _As_bytes = __iso_volatile_load64(_Mem);
	#endif
	_Load_barrier(_Order);
	return reinterpret_cast<_Ty&>(_As_bytes);
	}

[cbezault]

I'll study this and/or reach out to someone who might know if I can't reasonably answer.

[AlexGuteniev]

Might be related: IsProcessorFeaturePresent has option PF_ARM_64BIT_LOADSTORE_ATOMIC

[AlexGuteniev]

Another clue https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/5474/strd-atomic/13023

[AlexGuteniev]

In the case if it is right that only ldrexd has atomicity, but not ldrd for some CPUs, not sure if still need to support them, and if still need, __iso_volatile_store should be replaced with InterlockedExchange