From 2df2022c90e00c0eac542eba4078e79306155c7b Mon Sep 17 00:00:00 2001
From: Amr Hesham <amr96@programmer.net>
Date: Wed, 19 Feb 2025 22:06:12 +0100
Subject: [PATCH] [CIR][CIRGen][Builtin][Neon] Lower vgetq_lane_bf16, vduph f16
 and fb16 (#1372)

Lower vgetq_lane_bf16, vduph f16 and fb16
---
 .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp  |  3 ++-
 .../CodeGen/AArch64/bf16-getset-intrinsics.c  | 20 +++++++++++-------
 .../AArch64/v8.2a-neon-intrinsics-generic.c   | 21 +++++++++++--------
 3 files changed, 26 insertions(+), 18 deletions(-)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 9f6f94f295be..4db27337ced6 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -3909,7 +3909,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
   case NEON::BI__builtin_neon_vgetq_lane_bf16:
   case NEON::BI__builtin_neon_vduph_laneq_bf16:
   case NEON::BI__builtin_neon_vduph_laneq_f16: {
-    llvm_unreachable("NEON::BI__builtin_neon_vduph_laneq_f16 NYI");
+    return builder.create<cir::VecExtractOp>(getLoc(E->getExprLoc()), Ops[0],
+                                             emitScalarExpr(E->getArg(1)));
   }
   case NEON::BI__builtin_neon_vcvt_bf16_f32:
   case NEON::BI__builtin_neon_vcvtq_low_bf16_f32:
diff --git a/clang/test/CIR/CodeGen/AArch64/bf16-getset-intrinsics.c b/clang/test/CIR/CodeGen/AArch64/bf16-getset-intrinsics.c
index a8f643e82c5f..103a88dbcfc8 100644
--- a/clang/test/CIR/CodeGen/AArch64/bf16-getset-intrinsics.c
+++ b/clang/test/CIR/CodeGen/AArch64/bf16-getset-intrinsics.c
@@ -140,14 +140,18 @@ bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
   // LLVM: ret bfloat [[VGET_LANE]]
 }
 
-// CHECK-LABEL: @test_vgetq_lane_bf16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[VGETQ_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7
-// CHECK-NEXT:    ret bfloat [[VGETQ_LANE]]
-//
-// bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
-//   return vgetq_lane_bf16(v, 7);
-// }
+bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
+  return vgetq_lane_bf16(v, 7);
+
+  // CIR-LABEL: vgetq_lane_bf16
+  // CIR: [[TMP0:%.*]] = cir.const #cir.int<7> : !s32i
+  // CIR: [[TMP1:%.*]] = cir.vec.extract {{.*}}[{{.*}} : !s32i] : !cir.vector<!cir.bf16 x 8>
+
+  // LLVM-LABEL: test_vgetq_lane_bf16
+  // LLVM-SAME: (<8 x bfloat> [[VEC:%.*]])
+  // LLVM: [[VGET_LANE:%.*]] = extractelement <8 x bfloat> [[VEC]], i32 7
+  // LLVM: ret bfloat [[VGET_LANE]]
+}
 
 // CHECK-LABEL: @test_vset_lane_bf16(
 // CHECK-NEXT:  entry:
diff --git a/clang/test/CIR/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c b/clang/test/CIR/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
index 2de4862258a1..e06ac095d39b 100644
--- a/clang/test/CIR/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
+++ b/clang/test/CIR/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
@@ -471,15 +471,18 @@
 //   return vtrn2q_f16(a, b);
 // }
 
-// CHECK-LABEL: define {{[^@]+}}@test_vduph_laneq_f16
-// CHECK-SAME: (<8 x half> noundef [[VEC:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[VGETQ_LANE:%.*]] = extractelement <8 x half> [[VEC]], i32 7
-// CHECK-NEXT:    ret half [[VGETQ_LANE]]
-//
-// float16_t test_vduph_laneq_f16(float16x8_t vec) {
-//   return vduph_laneq_f16(vec, 7);
-// }
+float16_t test_vduph_laneq_f16(float16x8_t vec) {
+  return vduph_laneq_f16(vec, 7);
+
+  // CIR-LABEL: vduph_laneq_f16
+  // CIR: [[TMP0:%.*]] = cir.const #cir.int<7> : !s32i
+  // CIR: [[TMP1:%.*]] = cir.vec.extract {{.*}}[{{.*}} : !s32i] : !cir.vector<!cir.f16 x 8>
+
+  // LLVM-LABEL: test_vduph_laneq_f16
+  // LLVM-SAME: (<8 x half> [[VEC:%.*]])
+  // LLVM: [[VGET_LANE:%.*]] = extractelement <8 x half> [[VEC]], i32 7
+  // LLVM: ret half [[VGET_LANE]]
+}
 
 float16_t test_vduph_lane_f16(float16x4_t vec) {
   return vduph_lane_f16(vec, 3);