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[RTGTest] Add a few instructions
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include/circt/Dialect/RTGTest/IR/RTGTestOps.td

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Original file line numberDiff line numberDiff line change
@@ -63,3 +63,86 @@ def ConstantTestOp : RTGTestOp<"constant_test", [
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let assemblyFormat = "type($result) attr-dict";
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let hasFolder = 1;
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}
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//===- Instruction Formats -------------------------------------------------===//
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class InstFormatIOpBase<string mnemonic, int opcode7, int funct3>
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: RTGTestOp<mnemonic, [InstructionOpInterface]> {
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let arguments = (ins IntegerRegisterType:$rd,
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IntegerRegisterType:$rs,
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Imm12Type:$imm);
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let assemblyFormat = "$rd `,` $rs `,` $imm attr-dict";
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let extraClassDeclaration = [{
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static void printInstructionBinary(llvm::raw_ostream &os,
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ArrayRef<Attribute> operands) {
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FoldAdaptor adaptor(operands);
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auto binary = APInt(12, cast<Imm12Attr>(adaptor.getImm()).getValue())
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.concat(APInt(5, cast<rtg::RegisterAttrInterface>(
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adaptor.getRs()).getClassIndex()))
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.concat(APInt(3, }] # funct3 # [{))
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.concat(APInt(5, cast<rtg::RegisterAttrInterface>(
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adaptor.getRd()).getClassIndex()))
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.concat(APInt(7, }] # opcode7 # [{));
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SmallVector<char> str;
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binary.toStringUnsigned(str, 16);
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os << str;
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}
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static void printInstructionAssembly(llvm::raw_ostream &os,
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ArrayRef<Attribute> operands) {
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FoldAdaptor adaptor(operands);
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os << getOperationName().split('.').second << " "
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRd())
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.getRegisterAssembly()
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<< ", "
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<< cast<Imm12Attr>(adaptor.getImm()).getValue()
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<< "("
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRs())
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.getRegisterAssembly()
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<< ")";
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}
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}];
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}
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class InstFormatIImmOpBase<string mnemonic, int opcode7, int funct12>
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: RTGTestOp<mnemonic, [InstructionOpInterface]> {
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let assemblyFormat = "attr-dict";
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let extraClassDeclaration = [{
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static void printInstructionBinary(llvm::raw_ostream &os,
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ArrayRef<Attribute> operands) {
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auto binary = APInt(12, }] # funct12 # [{)
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.concat(APInt(13, 0))
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.concat(llvm::APInt(7, }] # opcode7 # [{));
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SmallVector<char> str;
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binary.toStringUnsigned(str, 16);
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os << str;
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}
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static void printInstructionAssembly(llvm::raw_ostream &os,
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ArrayRef<Attribute> operands) {
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os << getOperationName().split('.').second;
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}
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}];
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}
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//===- Instructions -------------------------------------------------------===//
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def JALROp : InstFormatIOpBase<"jalr", 0b1100111, 0b000>;
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def LBOp : InstFormatIOpBase<"lb", 0b0000011, 0b000>;
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def LHOp : InstFormatIOpBase<"lh", 0b0000011, 0b001>;
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def LWOp : InstFormatIOpBase<"lw", 0b0000011, 0b010>;
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def LBUOp : InstFormatIOpBase<"lbu", 0b0000011, 0b100>;
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def LHUOp : InstFormatIOpBase<"lhu", 0b0000011, 0b101>;
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def ECALLOp : InstFormatIImmOpBase<"ecall", 0b1110011, 0b000000000000>;
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def EBREAKOp : InstFormatIImmOpBase<"ebreak", 0b1110011, 0b000000000001>;

test/Dialect/RTGTest/IR/basic.mlir

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Original file line numberDiff line numberDiff line change
@@ -96,6 +96,28 @@ rtg.test @immediates : !rtg.dict<> {
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rtgtest.immediate #rtgtest.imm32<3> : !rtgtest.imm32
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}
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// CHECK-LABEL: @instructions
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rtg.test @instructions : !rtg.dict<imm: !rtgtest.imm12, rd: !rtgtest.ireg, rs: !rtgtest.ireg> {
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// CHECK: ([[IMM:%.+]]: !rtgtest.imm12, [[RD:%.+]]: !rtgtest.ireg, [[RS:%.+]]: !rtgtest.ireg)
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^bb0(%imm: !rtgtest.imm12, %rd: !rtgtest.ireg, %rs: !rtgtest.ireg):
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// CHECK: rtgtest.jalr [[RD]], [[RS]], [[IMM]]
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rtgtest.jalr %rd, %rs, %imm
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// CHECK: rtgtest.lb [[RD]], [[RS]], [[IMM]]
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rtgtest.lb %rd, %rs, %imm
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// CHECK: rtgtest.lh [[RD]], [[RS]], [[IMM]]
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rtgtest.lh %rd, %rs, %imm
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// CHECK: rtgtest.lw [[RD]], [[RS]], [[IMM]]
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rtgtest.lw %rd, %rs, %imm
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// CHECK: rtgtest.lbu [[RD]], [[RS]], [[IMM]]
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rtgtest.lbu %rd, %rs, %imm
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// CHECK: rtgtest.lhu [[RD]], [[RS]], [[IMM]]
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rtgtest.lhu %rd, %rs, %imm
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// CHECK: rtgtest.ecall
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rtgtest.ecall
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// CHECK: rtgtest.ebreak
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rtgtest.ebreak
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}
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// -----
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rtg.test @immediateTooBig : !rtg.dict<> {

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