This repository has been archived by the owner on Feb 4, 2023. It is now read-only.
-
Notifications
You must be signed in to change notification settings - Fork 23
/
Copy pathw5100_Impl.h
1117 lines (883 loc) · 26.1 KB
/
w5100_Impl.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/****************************************************************************************************************************
w5100_Impl.h - Driver for W5x00
Ethernet_Generic is a library for the W5x00 Ethernet shields trying to merge the good features of
previous Ethernet libraries
Based on and modified from
1) Ethernet Library https://github.com/arduino-libraries/Ethernet
2) EthernetLarge Library https://github.com/OPEnSLab-OSU/EthernetLarge
3) Ethernet2 Library https://github.com/adafruit/Ethernet2
4) Ethernet3 Library https://github.com/sstaub/Ethernet3
Built by Khoi Hoang https://github.com/khoih-prog/EthernetWebServer
Version: 2.6.0
Version Modified By Date Comments
------- ----------- ---------- -----------
2.0.0 K Hoang 31/03/2022 Initial porting and coding to support SPI2, debug, h-only library
2.0.1 K Hoang 08/04/2022 Add support to SPI1 for RP2040 using arduino-pico core
2.1.0 K Hoang 22/04/2022 Add support to WIZNet W5100S
2.2.0 K Hoang 02/05/2022 Add support to custom SPI for any board, such as STM32
2.3.0 K Hoang 03/05/2022 Add support to custom SPI for RP2040, Portenta_H7, etc. using Arduino-mbed core
2.3.1 K Hoang 21/05/2022 Add setHostname() and related functions
2.4.0 K Hoang 31/07/2022 Using raw_address() as default instead of private IPAddress data
2.4.1 K Hoang 25/08/2022 Auto-select SPI SS/CS pin according to board package
2.5.0 K Hoang 26/08/2022 Using raw_address() as default only for arduino-pico for compatibility
2.5.1 K Hoang 01/09/2022 Slow SPI clock for old W5100 shield using SAMD Zero
2.5.2 K Hoang 06/09/2022 Slow SPI clock only when necessary. Improve support for SAMD21
2.6.0 K Hoang 11/09/2022 Add support to AVR Dx (AVR128Dx, AVR64Dx, AVR32Dx, etc.) using DxCore
*****************************************************************************************************************************/
#pragma once
#ifndef W5100_IMPL_H_
#define W5100_IMPL_H_
#include <Arduino.h>
#include "Ethernet_Generic.hpp"
#if !defined(_ETG_LOGLEVEL_)
#define _ETG_LOGLEVEL_ 4
#endif
#include "Ethernet_Generic_Debug.h"
#include "w5100.h"
#define W5100_DEBUG 1
/***************************************************/
/** Default SS pin setting **/
/***************************************************/
// If variant.h or other headers specifically define the
// default SS pin for ethernet, use it.
#if defined(PIN_SPI_SS_ETHERNET_LIB)
#if !defined(SS_PIN_DEFAULT)
#define SS_PIN_DEFAULT PIN_SPI_SS_ETHERNET_LIB
#endif
#if (_ETG_LOGLEVEL_ > 3)
#warning w5100_Impl.h : Use PIN_SPI_SS_ETHERNET_LIB defined, change SS_PIN_DEFAULT to PIN_SPI_SS_ETHERNET_LIB
#endif
///////////////////////////
// MKR boards default to pin 5 for MKR ETH
// Pins 8-10 are MOSI/SCK/MISO on MRK, so don't use pin 10
#elif defined(USE_ARDUINO_MKR_PIN_LAYOUT) || defined(ARDUINO_SAMD_MKRZERO) || defined(ARDUINO_SAMD_MKR1000) || \
defined(ARDUINO_SAMD_MKRFox1200) || defined(ARDUINO_SAMD_MKRGSM1400) || defined(ARDUINO_SAMD_MKRWAN1300) || \
defined(ARDUINO_SAMD_MKRVIDOR4000)
#if !defined(SS_PIN_DEFAULT)
#define SS_PIN_DEFAULT 5
#endif
#if (_ETG_LOGLEVEL_ > 3)
#warning w5100_Impl.h : Use MKR, change SS_PIN_DEFAULT to 5
#endif
///////////////////////////
// For boards using AVR, assume shields with SS on pin 10
// will be used. This allows for Arduino Mega (where
// SS is pin 53) and Arduino Leonardo (where SS is pin 17)
// to work by default with Arduino Ethernet Shield R2 & R3.
#elif defined(__AVR__)
#if !defined(SS_PIN_DEFAULT)
#define SS_PIN_DEFAULT 10
#endif
#if (_ETG_LOGLEVEL_ > 3)
#warning w5100_Impl.h : Use __AVR__, change SS_PIN_DEFAULT to 10
#endif
///////////////////////////
// If variant.h or other headers define these names
// use them if none of the other cases match
#elif defined(PIN_SPI_SS)
#if defined(__SAMD21G18A__)
#if (_ETG_LOGLEVEL_ > 3)
//10 - 2 (6 conflict) all not OK for Nano 33 IoT !!! SPI corrupted???
#warning w5100_Impl.h : Use __SAMD21G18A__, change SS_PIN_DEFAULT to 10
#endif
#if !defined(SS_PIN_DEFAULT)
#define SS_PIN_DEFAULT 10
#endif
#else
#if !defined(SS_PIN_DEFAULT)
#define SS_PIN_DEFAULT PIN_SPI_SS
#endif
#if (_ETG_LOGLEVEL_ > 3)
#warning w5100_Impl.h : Use PIN_SPI_SS defined, change SS_PIN_DEFAULT to PIN_SPI_SS
#endif
#endif
///////////////////////////
#elif defined(CORE_SS0_PIN)
#if !defined(SS_PIN_DEFAULT)
#define SS_PIN_DEFAULT CORE_SS0_PIN
#endif
#if (_ETG_LOGLEVEL_ > 3)
#warning w5100_Impl.h : Use CORE_SS0_PIN defined, change SS_PIN_DEFAULT to CORE_SS0_PIN
#endif
///////////////////////////
//KH for ESP32
#elif defined(ESP32)
#if (_ETG_LOGLEVEL_ > 3)
//pin SS already defined in ESP32 as pin 5, don't use this as conflict with SPIFFS, EEPROM, etc.
// Use in GPIO22
#warning w5100_Impl.h : Use ESP32, change SS_PIN_DEFAULT to GPIO22, MOSI(23), MISO(19), SCK(18)
#endif
#if !defined(SS_PIN_DEFAULT)
#define SS_PIN_DEFAULT 22 //SS
#endif
///////////////////////////
//KH for ESP8266
#elif defined(ESP8266)
#if (_ETG_LOGLEVEL_ > 3)
//pin SS already defined in ESP8266 as pin 15. Conflict => Move to pin GPIO4 (D2)
#warning w5100_Impl.h : Use ESP8266, change SS_PIN_DEFAULT to SS(4), MOSI(13), MISO(12), SCK(14)
#endif
#if !defined(SS_PIN_DEFAULT)
#define SS_PIN_DEFAULT D2 // GPIO4, SS
#endif
///////////////////////////
// As a final fallback, use pin 10
#else
#if !defined(SS_PIN_DEFAULT)
#define SS_PIN_DEFAULT 10
#endif
#if (_ETG_LOGLEVEL_ > 3)
//KH
#warning w5100_Impl.h : Use fallback, change SS_PIN_DEFAULT to 10
#endif
#endif
/////////////////////////////////////////////////////////
// W5100 controller instance
EthernetChip_t W5100Class::chip = noChip;
//KH
EthernetChip_t W5100Class::altChip = noChip;
//////
uint8_t W5100Class::CH_BASE_MSB;
uint8_t W5100Class::ss_pin = SS_PIN_DEFAULT;
#ifdef ETHERNET_LARGE_BUFFERS
uint16_t W5100Class::SSIZE = 2048;
uint16_t W5100Class::SMASK = 0x07FF;
#endif
/////////////////////////////////////////////////////////
W5100Class W5100;
/////////////////////////////////////////////////////////
#if (ETHERNET_GENERIC_USING_SPI2)
#if(_ETG_LOGLEVEL_> 2)
#warning ETHERNET_GENERIC_USING_SPI2 in w5100_Impl.h
#endif
#if defined(ESP32)
SPIClass SPI2(HSPI);
SPIClass* pCUR_SPI = &SPI2;
#elif (ETHERNET_USE_RPIPICO && !defined(ARDUINO_ARCH_MBED))
// For arduino-pico core
// SPIClassRP2040(spi_inst_t *spi, pin_size_t rx, pin_size_t cs, pin_size_t sck, pin_size_t tx);
SPIClass* pCUR_SPI = (SPIClass*) &SPI1;
#define CUR_PIN_MISO PIN_SPI1_MISO
#define CUR_PIN_MOSI PIN_SPI1_MOSI
#define CUR_PIN_SCK PIN_SPI1_SCK
#define CUR_PIN_SS PIN_SPI1_SS
#elif (USING_CUSTOM_SPI)
#if ( defined(CUR_PIN_MOSI) && defined(CUR_PIN_MISO) && defined(CUR_PIN_SCK) && defined(CUR_PIN_SS) )
#if (SPI_NEW_INITIALIZED)
#if(_ETG_LOGLEVEL_> 2)
#warning ETHERNET_GENERIC_USING_SPI2 with SPI_NEW_INITIALIZED in w5100_Impl.h
#endif
#else
#if(_ETG_LOGLEVEL_> 2)
#warning ETHERNET_GENERIC_USING_SPI2 without SPI_NEW_INITIALIZED in w5100_Impl.h
#endif
#if defined(ARDUINO_ARCH_MBED)
// Don't create the instance with CUR_PIN_SS, or Ethernet not working
// Be careful, Mbed SPI ctor is so weird, reversing the order => MISO, MOSI, SCK
//arduino::MbedSPI::MbedSPI(int miso, int mosi, int sck)
SPIClass SPI_New(CUR_PIN_MISO, CUR_PIN_MOSI, CUR_PIN_SCK);
#else
// Don't create the instance with CUR_PIN_SS, or Ethernet not working
SPIClass SPI_New(CUR_PIN_MOSI, CUR_PIN_MISO, CUR_PIN_SCK);
#endif
#endif
SPIClass* pCUR_SPI = (SPIClass*) &SPI_New;
#else
#error You must define CUR_PIN_MOSI, CUR_PIN_MISO, CUR_PIN_SCK and CUR_PIN_SS
#endif
#endif
#else
#if(_ETG_LOGLEVEL_> 2)
#warning ETHERNET_GENERIC_USING_SPI in w5100_Impl.h
#endif
SPIClass* pCUR_SPI = &SPI;
#endif
////////////////////////////////////////////////////////////
// pointers and bitmasks for optimized SS pin
#if defined(__AVR__)
volatile uint8_t * W5100Class::ss_pin_reg;
uint8_t W5100Class::ss_pin_mask;
#elif defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__) || defined(__MK64FX512__)
volatile uint8_t * W5100Class::ss_pin_reg;
#elif defined(__IMXRT1062__)
volatile uint32_t * W5100Class::ss_pin_reg;
uint32_t W5100Class::ss_pin_mask;
#elif defined(__MKL26Z64__)
volatile uint8_t * W5100Class::ss_pin_reg;
uint8_t W5100Class::ss_pin_mask;
#elif defined(__SAM3X8E__) || defined(__SAM3A8C__) || defined(__SAM3A4C__)
volatile uint32_t * W5100Class::ss_pin_reg;
uint32_t W5100Class::ss_pin_mask;
#elif defined(__PIC32MX__)
volatile uint32_t * W5100Class::ss_pin_reg;
uint32_t W5100Class::ss_pin_mask;
#elif defined(ARDUINO_ARCH_ESP8266)
volatile uint32_t * W5100Class::ss_pin_reg;
uint32_t W5100Class::ss_pin_mask;
#elif defined(__SAMD21G18A__)
volatile uint32_t * W5100Class::ss_pin_reg;
uint32_t W5100Class::ss_pin_mask;
#if (_ETG_LOGLEVEL_ > 3)
#warning w5100_Impl.h : Use __SAMD21G18A__
#endif
#endif
////////////////////////////////////////////////////////////
uint8_t W5100Class::init(uint8_t socketNumbers, uint8_t new_ss_pin)
{
(void) socketNumbers;
uint8_t i;
if (initialized)
return 1;
// Many Ethernet shields have a CAT811 or similar reset chip
// connected to W5100 or W5200 chips. The W5200 will not work at
// all, and may even drive its MISO pin, until given an active low
// reset pulse! The CAT811 has a 240 ms typical pulse length, and
// a 400 ms worst case maximum pulse length. MAX811 has a worst
// case maximum 560 ms pulse length. This delay is meant to wait
// until the reset pulse is ended. If your hardware has a shorter
// reset time, this can be edited or removed.
delay(560);
//ETG_LOGWARN5("W5100 init, using SS_PIN_DEFAULT =", SS_PIN_DEFAULT, ", new ss_pin = ", new_ss_pin,
// ", W5100Class::ss_pin = ", W5100Class::ss_pin);
ETG_LOGWARN5("W5100 init, using W5100Class::ss_pin = ", W5100Class::ss_pin, ", whereas new ss_pin = ", new_ss_pin,
", SS_PIN_DEFAULT =", SS_PIN_DEFAULT);
pCUR_SPI->begin();
initSS();
resetSS();
// New
softReset();
//////
// From #define SPI_ETHERNET_SETTINGS SPISettings(14000000, MSBFIRST, SPI_MODE0)
beginSPITransaction();
// Attempt W5200 detection first, because W5200 does not properly
// reset its SPI state when CS goes high (inactive). Communication
// from detecting the other chips can leave the W5200 in a state
// where it won't recover, unless given a reset pulse.
if (isW5200())
{
CH_BASE_MSB = 0x40;
#ifdef ETHERNET_LARGE_BUFFERS
#if MAX_SOCK_NUM <= 1
SSIZE = 16384;
#elif MAX_SOCK_NUM <= 2
SSIZE = 8192;
#elif MAX_SOCK_NUM <= 4
SSIZE = 4096;
#else
SSIZE = 2048;
#endif
SMASK = SSIZE - 1;
#endif
for (i = 0; i < MAX_SOCK_NUM; i++)
{
writeSnRX_SIZE(i, SSIZE >> 10);
writeSnTX_SIZE(i, SSIZE >> 10);
}
for (; i < 8; i++)
{
writeSnRX_SIZE(i, 0);
writeSnTX_SIZE(i, 0);
}
ETG_LOGWARN1("W5100::init: W5200, SSIZE =", SSIZE);
// Try W5500 next. WIZnet finally seems to have implemented
// SPI well with this chip. It appears to be very resilient,
// so try it after the fragile W5200
}
else if (isW5500())
{
CH_BASE_MSB = 0x10;
#ifdef ETHERNET_LARGE_BUFFERS
#if MAX_SOCK_NUM <= 1
SSIZE = 16384;
#elif MAX_SOCK_NUM <= 2
SSIZE = 8192;
#elif MAX_SOCK_NUM <= 4
SSIZE = 4096;
#else
SSIZE = 2048;
#endif
SMASK = SSIZE - 1;
for (i = 0; i < MAX_SOCK_NUM; i++)
{
writeSnRX_SIZE(i, SSIZE >> 10);
writeSnTX_SIZE(i, SSIZE >> 10);
}
for (; i < 8; i++)
{
writeSnRX_SIZE(i, 0);
writeSnTX_SIZE(i, 0);
}
#endif
ETG_LOGWARN1("W5100::init: W5500, SSIZE =", SSIZE);
// Try W5100 last. This simple chip uses fixed 4 byte frames
// for every 8 bit access. Terribly inefficient, but so simple
// it recovers from "hearing" unsuccessful W5100 or W5200
// communication. W5100 is also the only chip without a VERSIONR
// register for identification, so we check this last.
}
else if (isW5100())
{
CH_BASE_MSB = 0x04;
#ifdef ETHERNET_LARGE_BUFFERS
#if MAX_SOCK_NUM <= 1
SSIZE = 8192;
writeTMSR(0x03);
writeRMSR(0x03);
#else
SSIZE = 4096;
writeTMSR(0x0A);
writeRMSR(0x0A);
#endif
SMASK = SSIZE - 1;
#else
writeTMSR(0x55);
writeRMSR(0x55);
#endif
ETG_LOGWARN1("W5100::init: W5100, SSIZE =", SSIZE);
// No hardware seems to be present. Or it could be a W5200
// that's heard other SPI communication if its chip select
// pin wasn't high when a SD card or other SPI chip was used.
}
else if (isW5100S())
{
CH_BASE_MSB = 0x04;
#ifdef ETHERNET_LARGE_BUFFERS
#if MAX_SOCK_NUM <= 1
SSIZE = 8192;
writeTMSR(0x03);
writeRMSR(0x03);
#else
SSIZE = 4096;
writeTMSR(0x0A);
writeRMSR(0x0A);
#endif
SMASK = SSIZE - 1;
#else
writeTMSR(0x55);
writeRMSR(0x55);
#endif
ETG_LOGWARN1("W5100::init: W5100S, SSIZE =", SSIZE);
// Try W5500 next. WIZnet finally seems to have implemented
// SPI well with this chip. It appears to be very resilient,
// so try it after the fragile W5200
}
else
{
ETG_LOGERROR("W5100::init: no chip :-(");
chip = noChip;
endSPITransaction();
return 0; // no known chip is responding :-(
}
endSPITransaction();
initialized = true;
return 1; // successful init
}
////////////////////////////////////////////////////////////
// Soft reset the WIZnet chip, by writing to its MR register reset bit
uint8_t W5100Class::softReset()
{
uint16_t count = 0;
ETG_LOGDEBUG("W5x00::softReset");
// write to reset bit
writeMR(0x80);
// then wait for soft reset to complete
do
{
uint8_t mr = readMR();
ETG_LOGDEBUG1("W5x00::softReset, mr =", mr);
if (mr == 0)
return 1;
delay(1);
} while (++count < 20);
return 0;
}
////////////////////////////////////////////////////////////
uint8_t W5100Class::isW5100()
{
chip = w5100;
ETG_LOGDEBUG("isW5100: detect W5100 chip");
if (!softReset())
return 0;
writeMR(0x10);
if (readMR() != 0x10)
return 0;
writeMR(0x12);
if (readMR() != 0x12)
return 0;
writeMR(0x00);
if (readMR() != 0x00)
return 0;
ETG_LOGWARN("Chip is W5100");
return 1;
}
////////////////////////////////////////////////////////////
uint8_t W5100Class::isW5100S()
{
chip = w5100s; // Must use w5100s before softReset()
// For other functions specific to W5100S, such as LinkStatus. etc
altChip = w5100s;
ETG_LOGDEBUG("isW5100S: detect W5100S chip");
if (!softReset())
return 0;
chip = w5100; // using w5100 after softReset() => read correct registers
writeMR(0x13);
if (readMR() != 0x13)
{
ETG_LOGDEBUG1("readMR (19) =", readMR());
return 0;
}
writeMR(0x1B);
if (readMR() != 0x1B)
{
ETG_LOGDEBUG1("readMR (27) =", readMR());
return 0;
}
writeMR(0x03);
if (readMR() != 0x03)
{
ETG_LOGDEBUG1("readMR (03) =", readMR());
return 0;
}
int ver = readVERSIONR_W5100S();
ETG_LOGDEBUG1("Version =", ver);
if (ver != 81)
return 0;
ETG_LOGWARN("Chip is W5100S");
return 1;
}
////////////////////////////////////////////////////////////
uint8_t W5100Class::isW5200()
{
chip = w5200;
ETG_LOGDEBUG("isW5200: detect W5200 chip");
if (!softReset())
return 0;
writeMR(0x08);
if (readMR() != 0x08)
return 0;
writeMR(0x10);
if (readMR() != 0x10)
return 0;
writeMR(0x00);
if (readMR() != 0x00)
return 0;
int ver = readVERSIONR_W5200();
ETG_LOGDEBUG1("Version =", ver);
if (ver != 3)
return 0;
ETG_LOGWARN("Chip is W5200");
return 1;
}
////////////////////////////////////////////////////////////
uint8_t W5100Class::isW5500()
{
chip = w5500;
ETG_LOGDEBUG("isW5500: detect W5500 chip");
if (!softReset())
return 0;
writeMR(0x08);
if (readMR() != 0x08)
return 0;
writeMR(0x10);
if (readMR() != 0x10)
return 0;
writeMR(0x00);
if (readMR() != 0x00)
return 0;
int ver = readVERSIONR_W5500();
ETG_LOGDEBUG1("Version =", ver);
if (ver != 4)
return 0;
ETG_LOGWARN("Chip is W5500");
return 1;
}
////////////////////////////////////////////////////////////
W5100Linkstatus W5100Class::getLinkStatus()
{
uint8_t phystatus;
if (!initialized)
return UNKNOWN;
switch (chip)
{
case w5200:
beginSPITransaction();
phystatus = readPSTATUS_W5200();
endSPITransaction();
if (phystatus & 0x20)
return LINK_ON;
return LINK_OFF;
case w5500:
beginSPITransaction();
phystatus = readPHYCFGR_W5500();
endSPITransaction();
if (phystatus & 0x01)
return LINK_ON;
return LINK_OFF;
default:
return UNKNOWN;
}
}
////////////////////////////////////////////////////////////
uint16_t W5100Class::write(uint16_t addr, const uint8_t *buf, uint16_t len)
{
uint8_t cmd[8];
if (chip == w5100)
{
for (uint16_t i = 0; i < len; i++)
{
setSS();
pCUR_SPI->transfer(0xF0);
pCUR_SPI->transfer(addr >> 8);
pCUR_SPI->transfer(addr & 0xFF);
addr++;
pCUR_SPI->transfer(buf[i]);
resetSS();
}
}
else if ( (chip == w5100s) )
{
setSS();
cmd[0] = addr >> 8;
cmd[1] = addr & 0xFF;
cmd[2] = ((len >> 8) & 0x7F) | 0x80;
cmd[3] = len & 0xFF;
pCUR_SPI->transfer(cmd, 4);
#ifdef SPI_HAS_TRANSFER_BUF
pCUR_SPI->transfer(buf, NULL, len);
#else
// TODO: copy 8 bytes at a time to cmd[] and block transfer
for (uint16_t i = 0; i < len; i++)
{
pCUR_SPI->transfer(buf[i]);
}
#endif
resetSS();
}
else if (chip == w5200)
{
setSS();
cmd[0] = addr >> 8;
cmd[1] = addr & 0xFF;
cmd[2] = ((len >> 8) & 0x7F) | 0x80;
cmd[3] = len & 0xFF;
pCUR_SPI->transfer(cmd, 4);
#ifdef SPI_HAS_TRANSFER_BUF
pCUR_SPI->transfer(buf, NULL, len);
#else
// TODO: copy 8 bytes at a time to cmd[] and block transfer
for (uint16_t i = 0; i < len; i++)
{
pCUR_SPI->transfer(buf[i]);
}
#endif
resetSS();
}
else
{
// chip == w5500
setSS();
if (addr < 0x100)
{
// common registers 00nn
cmd[0] = 0;
cmd[1] = addr & 0xFF;
cmd[2] = 0x04;
}
else if (addr < 0x8000)
{
// socket registers 10nn, 11nn, 12nn, 13nn, etc
cmd[0] = 0;
cmd[1] = addr & 0xFF;
cmd[2] = ((addr >> 3) & 0xE0) | 0x0C;
}
else if (addr < 0xC000)
{
// transmit buffers 8000-87FF, 8800-8FFF, 9000-97FF, etc
// 10## #nnn nnnn nnnn
cmd[0] = addr >> 8;
cmd[1] = addr & 0xFF;
#if defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 1
cmd[2] = 0x14; // 16K buffers
#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 2
cmd[2] = ((addr >> 8) & 0x20) | 0x14; // 8K buffers
#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 4
cmd[2] = ((addr >> 7) & 0x60) | 0x14; // 4K buffers
#else
cmd[2] = ((addr >> 6) & 0xE0) | 0x14; // 2K buffers
#endif
}
else
{
// receive buffers
cmd[0] = addr >> 8;
cmd[1] = addr & 0xFF;
#if defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 1
cmd[2] = 0x1C; // 16K buffers
#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 2
cmd[2] = ((addr >> 8) & 0x20) | 0x1C; // 8K buffers
#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 4
cmd[2] = ((addr >> 7) & 0x60) | 0x1C; // 4K buffers
#else
cmd[2] = ((addr >> 6) & 0xE0) | 0x1C; // 2K buffers
#endif
}
if (len <= 5)
{
for (uint8_t i = 0; i < len; i++)
{
cmd[i + 3] = buf[i];
}
pCUR_SPI->transfer(cmd, len + 3);
}
else
{
pCUR_SPI->transfer(cmd, 3);
#ifdef SPI_HAS_TRANSFER_BUF
pCUR_SPI->transfer(buf, NULL, len);
#else
// TODO: copy 8 bytes at a time to cmd[] and block transfer
for (uint16_t i = 0; i < len; i++)
{
pCUR_SPI->transfer(buf[i]);
}
#endif
}
resetSS();
}
return len;
}
////////////////////////////////////////////////////////////
uint16_t W5100Class::read(uint16_t addr, uint8_t *buf, uint16_t len)
{
uint8_t cmd[4];
if ( (chip == w5100))
{
for (uint16_t i = 0; i < len; i++)
{
setSS();
pCUR_SPI->transfer(0x0F);
pCUR_SPI->transfer(addr >> 8);
pCUR_SPI->transfer(addr & 0xFF);
addr++;
buf[i] = pCUR_SPI->transfer(0);
resetSS();
}
}
else if ( (chip == w5100s) )
{
setSS();
cmd[0] = addr >> 8;
cmd[1] = addr & 0xFF;
cmd[2] = (len >> 8) & 0x7F;
cmd[3] = len & 0xFF;
pCUR_SPI->transfer(cmd, 4);
memset(buf, 0, len);
pCUR_SPI->transfer(buf, len);
resetSS();
}
else if (chip == w5200)
{
setSS();
cmd[0] = addr >> 8;
cmd[1] = addr & 0xFF;
cmd[2] = (len >> 8) & 0x7F;
cmd[3] = len & 0xFF;
pCUR_SPI->transfer(cmd, 4);
memset(buf, 0, len);
pCUR_SPI->transfer(buf, len);
resetSS();
}
else
{
// chip == w5500
setSS();
if (addr < 0x100)
{
// common registers 00nn
cmd[0] = 0;
cmd[1] = addr & 0xFF;
cmd[2] = 0x00;
}
else if (addr < 0x8000)
{
// socket registers 10nn, 11nn, 12nn, 13nn, etc
cmd[0] = 0;
cmd[1] = addr & 0xFF;
cmd[2] = ((addr >> 3) & 0xE0) | 0x08;
}
else if (addr < 0xC000)
{
// transmit buffers 8000-87FF, 8800-8FFF, 9000-97FF, etc
// 10## #nnn nnnn nnnn
cmd[0] = addr >> 8;
cmd[1] = addr & 0xFF;
#if defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 1
cmd[2] = 0x10; // 16K buffers
#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 2
cmd[2] = ((addr >> 8) & 0x20) | 0x10; // 8K buffers
#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 4
cmd[2] = ((addr >> 7) & 0x60) | 0x10; // 4K buffers
#else
cmd[2] = ((addr >> 6) & 0xE0) | 0x10; // 2K buffers
#endif
}
else
{
// receive buffers
cmd[0] = addr >> 8;
cmd[1] = addr & 0xFF;
#if defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 1
cmd[2] = 0x18; // 16K buffers
#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 2
cmd[2] = ((addr >> 8) & 0x20) | 0x18; // 8K buffers
#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 4
cmd[2] = ((addr >> 7) & 0x60) | 0x18; // 4K buffers
#else
cmd[2] = ((addr >> 6) & 0xE0) | 0x18; // 2K buffers
#endif
}
pCUR_SPI->transfer(cmd, 3);
memset(buf, 0, len);
pCUR_SPI->transfer(buf, len);
resetSS();
}
return len;
}
////////////////////////////////////////////////////////////
// From Ethernet3
void W5100Class::phyMode(phyMode_t mode)
{
// Valid only for W5500
if (chip != w5500)
return;
uint8_t val = getPHYCFGR();
bitWrite(val, 6, 1);
if (mode == HALF_DUPLEX_10)
{
bitWrite(val, 3, 0);
bitWrite(val, 4, 0);
bitWrite(val, 5, 0);
setPHYCFGR(val);
}
else if (mode == FULL_DUPLEX_10)
{
bitWrite(val, 3, 1);
bitWrite(val, 4, 0);
bitWrite(val, 5, 0);
setPHYCFGR(val);
}
else if (mode == HALF_DUPLEX_100)
{
bitWrite(val, 3, 0);
bitWrite(val, 4, 1);
bitWrite(val, 5, 0);
setPHYCFGR(val);
}
else if (mode == FULL_DUPLEX_100)
{
bitWrite(val, 3, 1);
bitWrite(val, 4, 1);
bitWrite(val, 5, 0);
setPHYCFGR(val);
}
else if (mode == FULL_DUPLEX_100_AUTONEG)