From 9312c91c29415a9260a1c4e6d489e0fe11d6b1e4 Mon Sep 17 00:00:00 2001 From: Mike Field Date: Sat, 9 Mar 2019 11:40:12 +1300 Subject: [PATCH] Correct typo --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 2b45835..e46025e 100644 --- a/README.md +++ b/README.md @@ -7,9 +7,9 @@ DisplayPort is quite a complex protocol. This is a minimal Verilog implementation in the Verilog language. Hopefully this will inspire others to improve on this. -This has now been tested using one or two lanes, and 800x600, 720p +This has now been tested using one or two lanes, and 800x600, 720p and 1080p resolutions, but should work with four lanes and 4k resolutions -too. +too. YCC and 442 video support should be simple to add too. Status ======