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multiplier.map.rpt
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Analysis & Synthesis report for multiplier
Sat Jan 28 17:26:37 2012
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Registers Removed During Synthesis
8. General Register Statistics
9. Parameter Settings for User Entity Instance: bit_flips:inst|BUSMUX:inst42
10. Parameter Settings for User Entity Instance: bit_flips:inst|BUSMUX:inst41
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Jan 28 17:26:37 2012 ;
; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name ; multiplier ;
; Top-level Entity Name ; multiplier ;
; Family ; Cyclone ;
; Total logic elements ; 58 ;
; Total pins ; 56 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; DSP block 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; 0 ;
; Total DLLs ; N/A until Partition Merge ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device ; EP1C20F400C7 ; ;
; Top-level entity name ; multiplier ; multiplier ;
; Family name ; Cyclone ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+--------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------------------------------------+
; multiplier.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/multiplier.bdf ;
; state_machine.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/state_machine.bdf ;
; input_select.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/input_select.bdf ;
; bit_flips.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/bit_flips.bdf ;
; add_subt_decision.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/add_subt_decision.bdf ;
; add_subt_select.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/add_subt_select.bdf ;
; bus_combine.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/bus_combine.bdf ;
; np_register.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/np_register.bdf ;
; adder_subtractor.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/adder_subtractor.bdf ;
; simple_adder.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/simple_adder.bdf ;
; CLA_logic.bdf ; yes ; User Block Diagram/Schematic File ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/CLA_logic.bdf ;
; BUSMUX.tdf ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/BUSMUX.tdf ;
; lpm_mux.inc ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/lpm_mux.inc ;
; lpm_mux.tdf ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/lpm_mux.tdf ;
; aglobal80.inc ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/aglobal80.inc ;
; muxlut.inc ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/muxlut.inc ;
; bypassff.inc ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/altshift.inc ;
; db/mux_6fc.tdf ; yes ; Auto-Generated Megafunction ; E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/db/mux_6fc.tdf ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------------+
; Total logic elements ; 58 ;
; -- Combinational with no register ; 46 ;
; -- Register only ; 8 ;
; -- Combinational with a register ; 4 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 32 ;
; -- 3 input functions ; 12 ;
; -- 2 input functions ; 6 ;
; -- 1 input functions ; 0 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 58 ;
; -- arithmetic mode ; 0 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 3 ;
; ; ;
; Total registers ; 12 ;
; I/O pins ; 56 ;
; Maximum fan-out node ; np_register:inst16|inst7 ;
; Maximum fan-out ; 16 ;
; Total fan-out ; 245 ;
; Average fan-out ; 2.15 ;
+---------------------------------------------+--------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+--------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------+--------------+
; |multiplier ; 58 (2) ; 12 ; 0 ; 56 ; 0 ; 46 (1) ; 8 (0) ; 4 (1) ; 0 (0) ; 0 (0) ; |multiplier ; ;
; |add_subt_decision:inst14| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|add_subt_decision:inst14 ; work ;
; |add_subt_select:inst21| ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|add_subt_select:inst21 ; work ;
; |adder_subtractor:inst25| ; 11 (1) ; 0 ; 0 ; 0 ; 0 ; 11 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|adder_subtractor:inst25 ; work ;
; |CLA_logic:inst4| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|adder_subtractor:inst25|CLA_logic:inst4 ; work ;
; |simple_adder:inst3| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|adder_subtractor:inst25|simple_adder:inst3 ; work ;
; |simple_adder:inst7| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|adder_subtractor:inst25|simple_adder:inst7 ; work ;
; |simple_adder:inst9| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|adder_subtractor:inst25|simple_adder:inst9 ; work ;
; |bit_flips:inst| ; 14 (6) ; 0 ; 0 ; 0 ; 0 ; 14 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|bit_flips:inst ; work ;
; |busmux:inst41| ; 4 (0) ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|bit_flips:inst|busmux:inst41 ; work ;
; |lpm_mux:$00000| ; 4 (0) ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|bit_flips:inst|busmux:inst41|lpm_mux:$00000 ; work ;
; |mux_6fc:auto_generated| ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|bit_flips:inst|busmux:inst41|lpm_mux:$00000|mux_6fc:auto_generated ; work ;
; |busmux:inst42| ; 4 (0) ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|bit_flips:inst|busmux:inst42 ; work ;
; |lpm_mux:$00000| ; 4 (0) ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|bit_flips:inst|busmux:inst42|lpm_mux:$00000 ; work ;
; |mux_6fc:auto_generated| ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|bit_flips:inst|busmux:inst42|lpm_mux:$00000|mux_6fc:auto_generated ; work ;
; |input_select:inst9| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|input_select:inst9 ; work ;
; |np_register:inst16| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; |multiplier|np_register:inst16 ; work ;
; |state_machine:inst1| ; 8 (8) ; 3 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |multiplier|state_machine:inst1 ; work ;
+--------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+-------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+-------------------------------------+
; np_register:inst16|inst1 ; Merged with np_register:inst16|inst ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+-------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 12 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 3 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: bit_flips:inst|BUSMUX:inst42 ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------------+
; WIDTH ; 4 ; Untyped ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: bit_flips:inst|BUSMUX:inst41 ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------------+
; WIDTH ; 4 ; Untyped ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Sat Jan 28 17:26:28 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off multiplier -c multiplier
Warning: Can't analyze file -- file E:/DROPBOX/UNIVERSITY/YEAR 4/DIGITAL ELECTRONICS/ASSIGNMENTS 3 - PROCESSOR/MULTIPLIER_BLOCK/logic.tdf is missing
Info: Found 1 design units, including 1 entities, in source file multiplier.bdf
Info: Found entity 1: multiplier
Info: Found 1 design units, including 1 entities, in source file state_machine.bdf
Info: Found entity 1: state_machine
Info: Found 1 design units, including 1 entities, in source file p_register.bdf
Info: Found entity 1: p_register
Info: Found 1 design units, including 1 entities, in source file block_name.bdf
Info: Found entity 1: block_name
Info: Found 1 design units, including 1 entities, in source file input_select.bdf
Info: Found entity 1: input_select
Info: Found 1 design units, including 1 entities, in source file bit_flips.bdf
Info: Found entity 1: bit_flips
Info: Found 1 design units, including 1 entities, in source file add_subt_decision.bdf
Info: Found entity 1: add_subt_decision
Info: Found 1 design units, including 1 entities, in source file adder.bdf
Info: Found entity 1: adder
Info: Found 1 design units, including 1 entities, in source file add_subt_select.bdf
Info: Found entity 1: add_subt_select
Info: Found 1 design units, including 1 entities, in source file bus_combine.bdf
Info: Found entity 1: bus_combine
Info: Found 2 design units, including 1 entities, in source file lpm_add_sub0.vhd
Info: Found design unit 1: lpm_add_sub0-SYN
Info: Found entity 1: lpm_add_sub0
Info: Found 1 design units, including 1 entities, in source file temp_register.bdf
Info: Found entity 1: temp_register
Info: Found 1 design units, including 1 entities, in source file np_register.bdf
Info: Found entity 1: np_register
Info: Found 1 design units, including 1 entities, in source file adder_subtractor.bdf
Info: Found entity 1: adder_subtractor
Info: Found 1 design units, including 1 entities, in source file simple_adder.bdf
Info: Found entity 1: simple_adder
Info: Found 1 design units, including 1 entities, in source file CLA_logic.bdf
Info: Found entity 1: CLA_logic
Info: Found 2 design units, including 1 entities, in source file overflow_generate.vhd
Info: Found design unit 1: overflow_generate-overflow_generate_architecture
Info: Found entity 1: overflow_generate
Info: Elaborating entity "multiplier" for the top level hierarchy
Info: Elaborating entity "state_machine" for hierarchy "state_machine:inst1"
Info: Elaborating entity "add_subt_decision" for hierarchy "add_subt_decision:inst14"
Info: Elaborating entity "np_register" for hierarchy "np_register:inst16"
Info: Elaborating entity "input_select" for hierarchy "input_select:inst9"
Info: Elaborating entity "bus_combine" for hierarchy "bus_combine:inst19"
Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "old_data_in[0..4]"
Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "new_data_in[0..3]"
Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "data_out[0..8]"
Info: Elaborating entity "add_subt_select" for hierarchy "add_subt_select:inst21"
Info: Elaborating entity "adder_subtractor" for hierarchy "adder_subtractor:inst25"
Info: Elaborating entity "CLA_logic" for hierarchy "adder_subtractor:inst25|CLA_logic:inst4"
Info: Elaborating entity "simple_adder" for hierarchy "adder_subtractor:inst25|simple_adder:inst2"
Info: Elaborating entity "bit_flips" for hierarchy "bit_flips:inst"
Info: Elaborating entity "BUSMUX" for hierarchy "bit_flips:inst|BUSMUX:inst42"
Info: Elaborated megafunction instantiation "bit_flips:inst|BUSMUX:inst42"
Info: Instantiated megafunction "bit_flips:inst|BUSMUX:inst42" with the following parameter:
Info: Parameter "WIDTH" = "4"
Info: Elaborating entity "lpm_mux" for hierarchy "bit_flips:inst|BUSMUX:inst42|lpm_mux:$00000"
Info: Elaborated megafunction instantiation "bit_flips:inst|BUSMUX:inst42|lpm_mux:$00000", which is child of megafunction instantiation "bit_flips:inst|BUSMUX:inst42"
Info: Found 1 design units, including 1 entities, in source file db/mux_6fc.tdf
Info: Found entity 1: mux_6fc
Info: Elaborating entity "mux_6fc" for hierarchy "bit_flips:inst|BUSMUX:inst42|lpm_mux:$00000|mux_6fc:auto_generated"
Info: Duplicate registers merged to single register
Info (13350): Duplicate register "np_register:inst16|inst1" merged to single register "np_register:inst16|inst"
Info: Implemented 114 device resources after synthesis - the final resource count might be different
Info: Implemented 10 input pins
Info: Implemented 46 output pins
Info: Implemented 58 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 178 megabytes
Info: Processing ended: Sat Jan 28 17:26:38 2012
Info: Elapsed time: 00:00:10
Info: Total CPU time (on all processors): 00:00:05