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cpu.c
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/*
* TamaLIB - A hardware agnostic first-gen Tamagotchi emulation library
*
* Copyright (C) 2021 Jean-Christophe Rona <[email protected]>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include "cpu.h"
#include "hw.h"
#include "hal.h"
#define TICK_FREQUENCY 32768 // Hz
#define OSC1_FREQUENCY TICK_FREQUENCY // Hz
#define OSC3_FREQUENCY 1000000 // Hz
#define TIMER_2HZ_PERIOD (TICK_FREQUENCY/2) // in ticks
#define TIMER_4HZ_PERIOD (TICK_FREQUENCY/4) // in ticks
#define TIMER_8HZ_PERIOD (TICK_FREQUENCY/8) // in ticks
#define TIMER_16HZ_PERIOD (TICK_FREQUENCY/16) // in ticks
#define TIMER_32HZ_PERIOD (TICK_FREQUENCY/32) // in ticks
#define TIMER_64HZ_PERIOD (TICK_FREQUENCY/64) // in ticks
#define TIMER_128HZ_PERIOD (TICK_FREQUENCY/128) // in ticks
#define TIMER_256HZ_PERIOD (TICK_FREQUENCY/256) // in ticks
#define MASK_4B 0xF00
#define MASK_6B 0xFC0
#define MASK_7B 0xFE0
#define MASK_8B 0xFF0
#define MASK_10B 0xFFC
#define MASK_12B 0xFFF
#define PCS (pc & 0xFF)
#define PCSL (pc & 0xF)
#define PCSH ((pc >> 4) & 0xF)
#define PCP ((pc >> 8) & 0xF)
#define PCB ((pc >> 12) & 0x1)
#define TO_PC(bank, page, step) ((step & 0xFF) | ((page & 0xF) << 8) | (bank & 0x1) << 12)
#define NBP ((np >> 4) & 0x1)
#define NPP (np & 0xF)
#define TO_NP(bank, page) ((page & 0xF) | (bank & 0x1) << 4)
#define XHL (x & 0xFF)
#define XL (x & 0xF)
#define XH ((x >> 4) & 0xF)
#define XP ((x >> 8) & 0xF)
#define YHL (y & 0xFF)
#define YL (y & 0xF)
#define YH ((y >> 4) & 0xF)
#define YP ((y >> 8) & 0xF)
#define M(n) get_memory(n)
#define SET_M(n, v) set_memory(n, v)
#define RQ(i) get_rq(i)
#define SET_RQ(i, v) set_rq(i, v)
#define SPL (sp & 0xF)
#define SPH ((sp >> 4) & 0xF)
#define FLAG_C (0x1 << 0)
#define FLAG_Z (0x1 << 1)
#define FLAG_D (0x1 << 2)
#define FLAG_I (0x1 << 3)
#define C !!(flags & FLAG_C)
#define Z !!(flags & FLAG_Z)
#define D !!(flags & FLAG_D)
#define I !!(flags & FLAG_I)
#define SET_C() {flags |= FLAG_C;}
#define CLEAR_C() {flags &= ~FLAG_C;}
#define SET_Z() {flags |= FLAG_Z;}
#define CLEAR_Z() {flags &= ~FLAG_Z;}
#define SET_D() {flags |= FLAG_D;}
#define CLEAR_D() {flags &= ~FLAG_D;}
#define SET_I() {flags |= FLAG_I;}
#define CLEAR_I() {flags &= ~FLAG_I;}
#define REG_CLK_INT_FACTOR_FLAGS 0xF00
#define REG_SW_INT_FACTOR_FLAGS 0xF01
#define REG_PROG_INT_FACTOR_FLAGS 0xF02
#define REG_SERIAL_INT_FACTOR_FLAGS 0xF03
#define REG_K00_K03_INT_FACTOR_FLAGS 0xF04
#define REG_K10_K13_INT_FACTOR_FLAGS 0xF05
#define REG_CLOCK_INT_MASKS 0xF10
#define REG_SW_INT_MASKS 0xF11
#define REG_PROG_INT_MASKS 0xF12
#define REG_SERIAL_INT_MASKS 0xF13
#define REG_K00_K03_INT_MASKS 0xF14
#define REG_K10_K13_INT_MASKS 0xF15
#define REG_CLOCK_TIMER_DATA_1 0xF20
#define REG_CLOCK_TIMER_DATA_2 0xF21
#define REG_SW_TIMER_DATA_L 0xF22
#define REG_SW_TIMER_DATA_H 0xF23
#define REG_PROG_TIMER_DATA_L 0xF24
#define REG_PROG_TIMER_DATA_H 0xF25
#define REG_PROG_TIMER_RELOAD_DATA_L 0xF26
#define REG_PROG_TIMER_RELOAD_DATA_H 0xF27
#define REG_SERIAL_IF_DATA_L 0xF30
#define REG_SERIAL_IF_DATA_H 0xF31
#define REG_K00_K03_INPUT_PORT 0xF40
#define REG_K00_K03_INPUT_RELATION 0xF41
#define REG_K10_K13_INPUT_PORT 0xF42
#define REG_R00_R03_OUTPUT_PORT 0xF50
#define REG_R10_R13_OUTPUT_PORT 0xF51
#define REG_R20_R23_OUTPUT_PORT 0xF52
#define REG_R30_R33_OUTPUT_PORT 0xF53
#define REG_R40_R43_BZ_OUTPUT_PORT 0xF54
#define REG_P00_P03_IO_PORT 0xF60
#define REG_P10_P13_IO_PORT 0xF61
#define REG_P20_P23_IO_PORT 0xF62
#define REG_P30_P33_IO_PORT 0xF63
#define REG_CPU_OSC3_CTRL 0xF70
#define REG_LCD_CTRL 0xF71
#define REG_LCD_CONTRAST 0xF72
#define REG_SVD_CTRL 0xF73
#define REG_BUZZER_CTRL1 0xF74
#define REG_BUZZER_CTRL2 0xF75
#define REG_CLK_WD_TIMER_CTRL 0xF76
#define REG_SW_TIMER_CTRL 0xF77
#define REG_PROG_TIMER_CTRL 0xF78
#define REG_PROG_TIMER_CLK_SEL 0xF79
#define REG_SERIAL_IF_CLK_SEL 0xF7A
#define REG_HIGH_IMPEDANCE_OUTPUT_CTRL 0xF7B
#define REG_IO_CTRL 0xF7D
#define REG_IO_PULLUP_CFG 0xF7E
#define INPUT_PORT_NUM 2
typedef struct {
char *log;
u12_t code;
u12_t mask;
u12_t shift_arg0;
u12_t mask_arg0; // != 0 only if there are two arguments
u8_t cycles;
void (*cb)(u8_t arg0, u8_t arg1);
} op_t;
typedef struct {
u4_t states;
} input_port_t;
/* Registers */
static u13_t pc, next_pc;
static u12_t x, y;
static u4_t a, b;
static u5_t np;
static u8_t sp;
/* Flags */
static u4_t flags;
static const u12_t *g_program = NULL;
static MEM_BUFFER_TYPE memory[MEM_BUFFER_SIZE];
static input_port_t inputs[INPUT_PORT_NUM] = {{0}};
/* Interrupts (in priority order) */
static interrupt_t interrupts[INT_SLOT_NUM] = {
{0x0, 0x0, 0, 0x0C}, // Prog timer
{0x0, 0x0, 0, 0x0A}, // Serial interface
{0x0, 0x0, 0, 0x08}, // Input (K10-K13)
{0x0, 0x0, 0, 0x06}, // Input (K00-K03)
{0x0, 0x0, 0, 0x04}, // Stopwatch timer
{0x0, 0x0, 0, 0x02}, // Clock timer
};
static char *interrupt_names[] = {
[INT_PROG_TIMER_SLOT] = "INT_PROG_TIMER_SLOT",
[INT_SERIAL_SLOT] = "INT_SERIAL_SLOT",
[INT_K10_K13_SLOT] = "INT_K10_K13_SLOT",
[INT_K00_K03_SLOT] = "INT_K00_K03_SLOT",
[INT_STOPWATCH_SLOT] = "INT_STOPWATCH_SLOT",
[INT_CLOCK_TIMER_SLOT] = "INT_CLOCK_TIMER_SLOT",
};
static breakpoint_t *g_breakpoints = NULL;
static u32_t call_depth = 0;
static u32_t clk_timer_2hz_timestamp = 0; // in ticks
static u32_t clk_timer_4hz_timestamp = 0; // in ticks
static u32_t clk_timer_8hz_timestamp = 0; // in ticks
static u32_t clk_timer_16hz_timestamp = 0; // in ticks
static u32_t clk_timer_32hz_timestamp = 0; // in ticks
static u32_t clk_timer_64hz_timestamp = 0; // in ticks
static u32_t clk_timer_128hz_timestamp = 0; // in ticks
static u32_t clk_timer_256hz_timestamp = 0; // in ticks
static u32_t prog_timer_timestamp = 0; // in ticks
static bool_t prog_timer_enabled = 0;
static u8_t prog_timer_data = 0;
static u8_t prog_timer_rld = 0;
static u32_t tick_counter = 0;
static u32_t ts_freq;
static u8_t speed_ratio = 1;
static timestamp_t ref_ts;
static bool_t cpu_halted = 0;
static u32_t cpu_frequency = OSC1_FREQUENCY; // in hz
static u32_t scaled_cycle_accumulator = 0;
static state_t cpu_state = {
.pc = &pc,
.x = &x,
.y = &y,
.a = &a,
.b = &b,
.np = &np,
.sp = &sp,
.flags = &flags,
.tick_counter = &tick_counter,
.clk_timer_2hz_timestamp = &clk_timer_2hz_timestamp,
.clk_timer_4hz_timestamp = &clk_timer_4hz_timestamp,
.clk_timer_8hz_timestamp = &clk_timer_8hz_timestamp,
.clk_timer_16hz_timestamp = &clk_timer_16hz_timestamp,
.clk_timer_32hz_timestamp = &clk_timer_32hz_timestamp,
.clk_timer_64hz_timestamp = &clk_timer_64hz_timestamp,
.clk_timer_128hz_timestamp = &clk_timer_128hz_timestamp,
.clk_timer_256hz_timestamp = &clk_timer_256hz_timestamp,
.prog_timer_timestamp = &prog_timer_timestamp,
.prog_timer_enabled = &prog_timer_enabled,
.prog_timer_data = &prog_timer_data,
.prog_timer_rld = &prog_timer_rld,
.call_depth = &call_depth,
.interrupts = interrupts,
.cpu_halted = &cpu_halted,
.memory = memory,
};
void cpu_add_bp(breakpoint_t **list, u13_t addr)
{
breakpoint_t *bp;
bp = (breakpoint_t *) g_hal->malloc(sizeof(breakpoint_t));
if (!bp) {
g_hal->log(LOG_ERROR, "Cannot allocate memory for breakpoint 0x%04X!\n", addr);
return;
}
bp->addr = addr;
if (*list != NULL) {
bp->next = *list;
} else {
/* List is empty */
bp->next = NULL;
}
*list = bp;
}
void cpu_free_bp(breakpoint_t **list)
{
breakpoint_t *bp = *list, *tmp;
while (bp != NULL) {
tmp = bp->next;
g_hal->free(bp);
bp = tmp;
}
*list = NULL;
}
void cpu_set_speed(u8_t speed)
{
speed_ratio = speed;
}
state_t * cpu_get_state(void)
{
return &cpu_state;
}
u32_t cpu_get_depth(void)
{
return call_depth;
}
static void generate_interrupt(int_slot_t slot, u8_t bit)
{
/* Set the factor flag no matter what */
interrupts[slot].factor_flag_reg = interrupts[slot].factor_flag_reg | (0x1 << bit);
/* Trigger the INT only if not masked */
if (interrupts[slot].mask_reg & (0x1 << bit)) {
interrupts[slot].triggered = 1;
}
}
void cpu_set_input_pin(pin_t pin, pin_state_t state)
{
u4_t old_state = (inputs[pin & 0x4].states >> (pin & 0x3)) & 0x1;
/* Trigger the interrupt if the state changed */
if (state != old_state) {
switch ((pin & 0x4) >> 2) {
case 0:
/* Active HIGH/LOW depending on the relation register */
if (state != ((GET_IO_MEMORY(memory, REG_K00_K03_INPUT_RELATION) >> (pin & 0x3)) & 0x1)) {
generate_interrupt(INT_K00_K03_SLOT, pin & 0x3);
}
break;
case 1:
/* Active LOW */
if (state == PIN_STATE_LOW) {
generate_interrupt(INT_K10_K13_SLOT, pin & 0x3);
}
break;
}
}
/* Set the I/O */
inputs[pin & 0x4].states = (inputs[pin & 0x4].states & ~(0x1 << (pin & 0x3))) | (state << (pin & 0x3));
}
void cpu_sync_ref_timestamp(void)
{
ref_ts = g_hal->get_timestamp();
}
static u4_t get_io(u12_t n)
{
u4_t tmp;
switch (n) {
case REG_CLK_INT_FACTOR_FLAGS:
/* Interrupt factor flags (clock timer) */
tmp = interrupts[INT_CLOCK_TIMER_SLOT].factor_flag_reg;
interrupts[INT_CLOCK_TIMER_SLOT].factor_flag_reg = 0;
return tmp;
case REG_SW_INT_FACTOR_FLAGS:
/* Interrupt factor flags (stopwatch) */
tmp = interrupts[INT_STOPWATCH_SLOT].factor_flag_reg;
interrupts[INT_STOPWATCH_SLOT].factor_flag_reg = 0;
return tmp;
case REG_PROG_INT_FACTOR_FLAGS:
/* Interrupt factor flags (prog timer) */
tmp = interrupts[INT_PROG_TIMER_SLOT].factor_flag_reg;
interrupts[INT_PROG_TIMER_SLOT].factor_flag_reg = 0;
return tmp;
case REG_SERIAL_INT_FACTOR_FLAGS:
/* Interrupt factor flags (serial) */
tmp = interrupts[INT_SERIAL_SLOT].factor_flag_reg;
interrupts[INT_SERIAL_SLOT].factor_flag_reg = 0;
return tmp;
case REG_K00_K03_INT_FACTOR_FLAGS:
/* Interrupt factor flags (K00-K03) */
tmp = interrupts[INT_K00_K03_SLOT].factor_flag_reg;
interrupts[INT_K00_K03_SLOT].factor_flag_reg = 0;
return tmp;
case REG_K10_K13_INT_FACTOR_FLAGS:
/* Interrupt factor flags (K10-K13) */
tmp = interrupts[INT_K10_K13_SLOT].factor_flag_reg;
interrupts[INT_K10_K13_SLOT].factor_flag_reg = 0;
return tmp;
case REG_CLOCK_INT_MASKS:
/* Clock timer interrupt masks */
return interrupts[INT_CLOCK_TIMER_SLOT].mask_reg;
case REG_SW_INT_MASKS:
/* Stopwatch interrupt masks */
return interrupts[INT_STOPWATCH_SLOT].mask_reg & 0x3;
case REG_PROG_INT_MASKS:
/* Prog timer interrupt masks */
return interrupts[INT_PROG_TIMER_SLOT].mask_reg & 0x1;
case REG_SERIAL_INT_MASKS:
/* Serial interface interrupt masks */
return interrupts[INT_SERIAL_SLOT].mask_reg & 0x1;
case REG_K00_K03_INT_MASKS:
/* Input (K00-K03) interrupt masks */
return interrupts[INT_K00_K03_SLOT].mask_reg;
case REG_K10_K13_INT_MASKS:
/* Input (K10-K13) interrupt masks */
return interrupts[INT_K10_K13_SLOT].mask_reg;
case REG_CLOCK_TIMER_DATA_1:
/* Clock timer data (16-128Hz) */
return GET_IO_MEMORY(memory, n);
case REG_CLOCK_TIMER_DATA_2:
/* Clock timer data (1-8Hz) */
return GET_IO_MEMORY(memory, n);
case REG_PROG_TIMER_DATA_L:
/* Prog timer data (low) */
return prog_timer_data & 0xF;
case REG_PROG_TIMER_DATA_H:
/* Prog timer data (high) */
return (prog_timer_data >> 4) & 0xF;
case REG_PROG_TIMER_RELOAD_DATA_L:
/* Prog timer reload data (low) */
return prog_timer_rld & 0xF;
case REG_PROG_TIMER_RELOAD_DATA_H:
/* Prog timer reload data (high) */
return (prog_timer_rld >> 4) & 0xF;
case REG_K00_K03_INPUT_PORT:
/* Input port (K00-K03) */
return inputs[0].states;
case REG_K00_K03_INPUT_RELATION:
/* Input relation register (K00-K03) */
return GET_IO_MEMORY(memory, n);
case REG_K10_K13_INPUT_PORT:
/* Input port (K10-K13) */
return inputs[1].states;
case REG_R40_R43_BZ_OUTPUT_PORT:
/* Output port (R40-R43) */
return GET_IO_MEMORY(memory, n);
case REG_CPU_OSC3_CTRL:
/* CPU/OSC3 clocks switch, CPU voltage switch */
return GET_IO_MEMORY(memory, n);
case REG_LCD_CTRL:
/* LCD control */
return GET_IO_MEMORY(memory, n);
case REG_LCD_CONTRAST:
/* LCD contrast */
break;
case REG_SVD_CTRL:
/* SVD */
return GET_IO_MEMORY(memory, n) & 0x7; // Voltage always OK
case REG_BUZZER_CTRL1:
/* Buzzer config 1 */
return GET_IO_MEMORY(memory, n);
case REG_BUZZER_CTRL2:
/* Buzzer config 2 */
return GET_IO_MEMORY(memory, n) & 0x3; // Buzzer ready
case REG_CLK_WD_TIMER_CTRL:
/* Clock/Watchdog timer reset */
break;
case REG_SW_TIMER_CTRL:
/* Stopwatch stop/run/reset */
break;
case REG_PROG_TIMER_CTRL:
/* Prog timer stop/run/reset */
return !!prog_timer_enabled;
case REG_PROG_TIMER_CLK_SEL:
/* Prog timer clock selection */
break;
default:
g_hal->log(LOG_ERROR, "Read from unimplemented I/O 0x%03X - PC = 0x%04X\n", n, pc);
}
return 0;
}
static void set_io(u12_t n, u4_t v)
{
switch (n) {
case REG_CLOCK_INT_MASKS:
/* Clock timer interrupt masks */
interrupts[INT_CLOCK_TIMER_SLOT].mask_reg = v;
break;
case REG_SW_INT_MASKS:
/* Stopwatch interrupt masks */
/* Assume all INT disabled */
interrupts[INT_STOPWATCH_SLOT].mask_reg = v;
break;
case REG_PROG_INT_MASKS:
/* Prog timer interrupt masks */
/* Assume Prog timer INT enabled (0x1) */
interrupts[INT_PROG_TIMER_SLOT].mask_reg = v;
break;
case REG_SERIAL_INT_MASKS:
/* Serial interface interrupt masks */
/* Assume all INT disabled */
interrupts[INT_K10_K13_SLOT].mask_reg = v;
break;
case REG_K00_K03_INT_MASKS:
/* Input (K00-K03) interrupt masks */
/* Assume all INT disabled */
interrupts[INT_SERIAL_SLOT].mask_reg = v;
break;
case REG_K10_K13_INT_MASKS:
/* Input (K10-K13) interrupt masks */
/* Assume all INT disabled */
interrupts[INT_K10_K13_SLOT].mask_reg = v;
break;
case REG_CLOCK_TIMER_DATA_1:
/* Write not allowed */
/* Clock timer data (16-128Hz) */
break;
case REG_CLOCK_TIMER_DATA_2:
/* Write not allowed */
/* Clock timer data (1-8Hz) */
break;
case REG_PROG_TIMER_RELOAD_DATA_L:
/* Prog timer reload data (low) */
prog_timer_rld = v | (prog_timer_rld & 0xF0);
break;
case REG_PROG_TIMER_RELOAD_DATA_H:
/* Prog timer reload data (high) */
prog_timer_rld = (prog_timer_rld & 0xF) | (v << 4);
break;
case REG_K00_K03_INPUT_PORT:
/* Input port (K00-K03) */
/* Write not allowed */
break;
case REG_K00_K03_INPUT_RELATION:
/* Input relation register (K00-K03) */
break;
case REG_R40_R43_BZ_OUTPUT_PORT:
/* Output port (R40-R43) */
//g_hal->log(LOG_INFO, "Output/Buzzer: 0x%X\n", v);
hw_enable_buzzer(!(v & 0x8));
break;
case REG_CPU_OSC3_CTRL:
/* CPU/OSC3 clocks switch, CPU voltage switch */
/* Do not care about OSC3 state nor operating voltage */
if ((v & 0x8) && cpu_frequency != OSC3_FREQUENCY) {
/* OSC3 */
cpu_frequency = OSC3_FREQUENCY;
scaled_cycle_accumulator = 0;
//g_hal->log(LOG_INFO, "Switch to OSC3\n");
}
if (!(v & 0x8) && cpu_frequency != OSC1_FREQUENCY) {
/* OSC1 */
cpu_frequency = OSC1_FREQUENCY;
scaled_cycle_accumulator = 0;
//g_hal->log(LOG_INFO, "Switch to OSC1\n");
}
break;
case REG_LCD_CTRL:
/* LCD control */
break;
case REG_LCD_CONTRAST:
/* LCD contrast */
/* Assume medium contrast (0x8) */
break;
case REG_SVD_CTRL:
/* SVD */
/* Assume battery voltage always OK (0x6) */
break;
case REG_BUZZER_CTRL1:
/* Buzzer config 1 */
hw_set_buzzer_freq(v & 0x7);
break;
case REG_BUZZER_CTRL2:
/* Buzzer config 2 */
break;
case REG_CLK_WD_TIMER_CTRL:
/* Clock/Watchdog timer reset */
/* Ignore watchdog */
break;
case REG_SW_TIMER_CTRL:
/* Stopwatch stop/run/reset */
break;
case REG_PROG_TIMER_CTRL:
/* Prog timer stop/run/reset */
if (v & 0x2) {
prog_timer_data = prog_timer_rld;
}
if ((v & 0x1) && !prog_timer_enabled) {
prog_timer_timestamp = tick_counter;
}
prog_timer_enabled = v & 0x1;
break;
case REG_PROG_TIMER_CLK_SEL:
/* Prog timer clock selection */
/* Assume 256Hz, output disabled */
break;
default:
g_hal->log(LOG_ERROR, "Write 0x%X to unimplemented I/O 0x%03X - PC = 0x%04X\n", v, n, pc);
}
}
static void set_lcd(u12_t n, u4_t v)
{
u8_t i;
u8_t seg, com0;
seg = ((n & 0x7F) >> 1);
com0 = (((n & 0x80) >> 7) * 8 + (n & 0x1) * 4);
for (i = 0; i < 4; i++) {
hw_set_lcd_pin(seg, com0 + i, (v >> i) & 0x1);
}
}
static u4_t get_memory(u12_t n)
{
u4_t res = 0;
if (n < MEM_RAM_SIZE) {
/* RAM */
g_hal->log(LOG_MEMORY, "RAM - ");
res = GET_RAM_MEMORY(memory, n);
} else if (n >= MEM_DISPLAY1_ADDR && n < (MEM_DISPLAY1_ADDR + MEM_DISPLAY1_SIZE)) {
/* Display Memory 1 */
g_hal->log(LOG_MEMORY, "Display Memory 1 - ");
res = GET_DISP1_MEMORY(memory, n);
} else if (n >= MEM_DISPLAY2_ADDR && n < (MEM_DISPLAY2_ADDR + MEM_DISPLAY2_SIZE)) {
/* Display Memory 2 */
g_hal->log(LOG_MEMORY, "Display Memory 2 - ");
res = GET_DISP2_MEMORY(memory, n);
} else if (n >= MEM_IO_ADDR && n < (MEM_IO_ADDR + MEM_IO_SIZE)) {
/* I/O Memory */
g_hal->log(LOG_MEMORY, "I/O - ");
res = get_io(n);
} else {
g_hal->log(LOG_ERROR, "Read from invalid memory address 0x%03X - PC = 0x%04X\n", n, pc);
return 0;
}
g_hal->log(LOG_MEMORY, "Read 0x%X - Address 0x%03X - PC = 0x%04X\n", res, n, pc);
return res;
}
static void set_memory(u12_t n, u4_t v)
{
/* Cache any data written to a valid address, and process it */
if (n < MEM_RAM_SIZE) {
/* RAM */
SET_RAM_MEMORY(memory, n, v);
g_hal->log(LOG_MEMORY, "RAM - ");
} else if (n >= MEM_DISPLAY1_ADDR && n < (MEM_DISPLAY1_ADDR + MEM_DISPLAY1_SIZE)) {
/* Display Memory 1 */
SET_DISP1_MEMORY(memory, n, v);
set_lcd(n, v);
g_hal->log(LOG_MEMORY, "Display Memory 1 - ");
} else if (n >= MEM_DISPLAY2_ADDR && n < (MEM_DISPLAY2_ADDR + MEM_DISPLAY2_SIZE)) {
/* Display Memory 2 */
SET_DISP2_MEMORY(memory, n, v);
set_lcd(n, v);
g_hal->log(LOG_MEMORY, "Display Memory 2 - ");
} else if (n >= MEM_IO_ADDR && n < (MEM_IO_ADDR + MEM_IO_SIZE)) {
/* I/O Memory */
SET_IO_MEMORY(memory, n, v);
set_io(n, v);
g_hal->log(LOG_MEMORY, "I/O - ");
} else {
g_hal->log(LOG_ERROR, "Write 0x%X to invalid memory address 0x%03X - PC = 0x%04X\n", v, n, pc);
return;
}
g_hal->log(LOG_MEMORY, "Write 0x%X - Address 0x%03X - PC = 0x%04X\n", v, n, pc);
}
void cpu_refresh_hw(void)
{
static const struct range {
u12_t addr;
u12_t size;
} refresh_locs[] = {
{ MEM_DISPLAY1_ADDR, MEM_DISPLAY1_SIZE }, /* Display Memory 1 */
{ MEM_DISPLAY2_ADDR, MEM_DISPLAY2_SIZE }, /* Display Memory 2 */
{ REG_BUZZER_CTRL1, 1 }, /* Buzzer frequency */
{ REG_R40_R43_BZ_OUTPUT_PORT, 1 }, /* Buzzer enabled */
{ 0, 0 }, // end of list
};
for (int i = 0; refresh_locs[i].size != 0; i++) {
for (u12_t n = refresh_locs[i].addr; n < (refresh_locs[i].addr + refresh_locs[i].size); n++) {
set_memory(n, GET_MEMORY(memory, n));
}
}
}
static u4_t get_rq(u12_t rq)
{
switch (rq & 0x3) {
case 0x0:
return a;
case 0x1:
return b;
case 0x2:
return M(x);
case 0x3:
return M(y);
}
return 0;
}
static void set_rq(u12_t rq, u4_t v)
{
switch (rq & 0x3) {
case 0x0:
a = v;
break;
case 0x1:
b = v;
break;
case 0x2:
SET_M(x, v);
break;
case 0x3:
SET_M(y, v);
break;
}
}
/* Instructions */
static void op_pset_cb(u8_t arg0, u8_t arg1)
{
np = arg0;
}
static void op_jp_cb(u8_t arg0, u8_t arg1)
{
next_pc = arg0 | (np << 8);
}
static void op_jp_c_cb(u8_t arg0, u8_t arg1)
{
if (flags & FLAG_C) {
next_pc = arg0 | (np << 8);
}
}
static void op_jp_nc_cb(u8_t arg0, u8_t arg1)
{
if (!(flags & FLAG_C)) {
next_pc = arg0 | (np << 8);
}
}
static void op_jp_z_cb(u8_t arg0, u8_t arg1)
{
if (flags & FLAG_Z) {
next_pc = arg0 | (np << 8);
}
}
static void op_jp_nz_cb(u8_t arg0, u8_t arg1)
{
if (!(flags & FLAG_Z)) {
next_pc = arg0 | (np << 8);
}
}
static void op_jpba_cb(u8_t arg0, u8_t arg1)
{
next_pc = a | (b << 4) | (np << 8);
}
static void op_call_cb(u8_t arg0, u8_t arg1)
{
pc = (pc + 1) & 0x1FFF; // This does not actually change the PC register
SET_M((sp - 1) & 0xFF, PCP);
SET_M((sp - 2) & 0xFF, PCSH);
SET_M((sp - 3) & 0xFF, PCSL);
sp = (sp - 3) & 0xFF;
next_pc = TO_PC(PCB, NPP, arg0);
call_depth++;
}
static void op_calz_cb(u8_t arg0, u8_t arg1)
{
pc = (pc + 1) & 0x1FFF; // This does not actually change the PC register
SET_M((sp - 1) & 0xFF, PCP);
SET_M((sp - 2) & 0xFF, PCSH);
SET_M((sp - 3) & 0xFF, PCSL);
sp = (sp - 3) & 0xFF;
next_pc = TO_PC(PCB, 0, arg0);
call_depth++;
}
static void op_ret_cb(u8_t arg0, u8_t arg1)
{
next_pc = M(sp) | (M((sp + 1) & 0xFF) << 4) | (M((sp + 2) & 0xFF) << 8) | (PCB << 12);
sp = (sp + 3) & 0xFF;
if (call_depth > 0) {
call_depth--;
}
}
static void op_rets_cb(u8_t arg0, u8_t arg1)
{
next_pc = M(sp) | (M((sp + 1) & 0xFF) << 4) | (M((sp + 2) & 0xFF) << 8) | (PCB << 12);
sp = (sp + 3) & 0xFF;
next_pc = (next_pc + 1) & 0x1FFF;
if (call_depth > 0) {
call_depth--;
}
}
static void op_retd_cb(u8_t arg0, u8_t arg1)
{
next_pc = M(sp) | (M((sp + 1) & 0xFF) << 4) | (M((sp + 2) & 0xFF) << 8) | (PCB << 12);
sp = (sp + 3) & 0xFF;
SET_M(x, arg0 & 0xF);
SET_M(((x + 1) & 0xFF) | (XP << 8), (arg0 >> 4) & 0xF);
x = ((x + 2) & 0xFF) | (XP << 8);
if (call_depth > 0) {
call_depth--;
}
}
static void op_nop5_cb(u8_t arg0, u8_t arg1)
{
}
static void op_nop7_cb(u8_t arg0, u8_t arg1)
{
}
static void op_halt_cb(u8_t arg0, u8_t arg1)
{
cpu_halted = 1;
}
static void op_inc_x_cb(u8_t arg0, u8_t arg1)
{
x = ((x + 1) & 0xFF) | (XP << 8);
}
static void op_inc_y_cb(u8_t arg0, u8_t arg1)
{
y = ((y + 1) & 0xFF) | (YP << 8);
}
static void op_ld_x_cb(u8_t arg0, u8_t arg1)
{
x = arg0 | (XP << 8);
}
static void op_ld_y_cb(u8_t arg0, u8_t arg1)
{
y = arg0 | (YP << 8);
}
static void op_ld_xp_r_cb(u8_t arg0, u8_t arg1)
{
x = XHL | (RQ(arg0) << 8);
}
static void op_ld_xh_r_cb(u8_t arg0, u8_t arg1)
{
x = XL | (RQ(arg0) << 4) | (XP << 8);
}
static void op_ld_xl_r_cb(u8_t arg0, u8_t arg1)
{
x = RQ(arg0) | (XH << 4) | (XP << 8);
}
static void op_ld_yp_r_cb(u8_t arg0, u8_t arg1)
{
y = YHL | (RQ(arg0) << 8);
}
static void op_ld_yh_r_cb(u8_t arg0, u8_t arg1)
{
y = YL | (RQ(arg0) << 4) | (YP << 8);
}
static void op_ld_yl_r_cb(u8_t arg0, u8_t arg1)
{
y = RQ(arg0) | (YH << 4) | (YP << 8);
}
static void op_ld_r_xp_cb(u8_t arg0, u8_t arg1)
{
SET_RQ(arg0, XP);
}
static void op_ld_r_xh_cb(u8_t arg0, u8_t arg1)
{
SET_RQ(arg0, XH);
}
static void op_ld_r_xl_cb(u8_t arg0, u8_t arg1)
{
SET_RQ(arg0, XL);
}
static void op_ld_r_yp_cb(u8_t arg0, u8_t arg1)
{
SET_RQ(arg0, YP);
}
static void op_ld_r_yh_cb(u8_t arg0, u8_t arg1)
{
SET_RQ(arg0, YH);
}
static void op_ld_r_yl_cb(u8_t arg0, u8_t arg1)
{
SET_RQ(arg0, YL);
}
static void op_adc_xh_cb(u8_t arg0, u8_t arg1)
{
u8_t tmp;
tmp = XH + arg0 + C;
x = XL | ((tmp & 0xF) << 4)| (XP << 8);
if (tmp >> 4) { SET_C(); } else { CLEAR_C(); }
if (!(tmp & 0xF)) { SET_Z(); } else { CLEAR_Z(); }
}
static void op_adc_xl_cb(u8_t arg0, u8_t arg1)
{
u8_t tmp;
tmp = XL + arg0 + C;
x = (tmp & 0xF) | (XH << 4) | (XP << 8);
if (tmp >> 4) { SET_C(); } else { CLEAR_C(); }
if (!(tmp & 0xF)) { SET_Z(); } else { CLEAR_Z(); }
}
static void op_adc_yh_cb(u8_t arg0, u8_t arg1)
{
u8_t tmp;
tmp = YH + arg0 + C;
y = YL | ((tmp & 0xF) << 4)| (YP << 8);
if (tmp >> 4) { SET_C(); } else { CLEAR_C(); }
if (!(tmp & 0xF)) { SET_Z(); } else { CLEAR_Z(); }
}
static void op_adc_yl_cb(u8_t arg0, u8_t arg1)
{
u8_t tmp;
tmp = YL + arg0 + C;
y = (tmp & 0xF) | (YH << 4) | (YP << 8);
if (tmp >> 4) { SET_C(); } else { CLEAR_C(); }
if (!(tmp & 0xF)) { SET_Z(); } else { CLEAR_Z(); }
}