From bab7803b43c022b2383ea27d64193f15e5ffa6bd Mon Sep 17 00:00:00 2001 From: Kiva Date: Tue, 2 Apr 2024 10:18:38 +0800 Subject: [PATCH] [Clang][XTHeadVector] Implement 13.5 vnclip/vnclipu (#90) * [Clang][XTHeadVector] Implement 13.5 `vnclip/vnclipu` * [Clang][XTHeadVector] Implement 13.5 `vnclip/vnclipu` wrapper macros --- .../clang/Basic/riscv_vector_xtheadv.td | 48 +++ .../Basic/riscv_vector_xtheadv_wrappers.td | 84 ++++ .../thead/vnclip.c | 367 ++++++++++++++++++ .../thead/vnclipu.c | 367 ++++++++++++++++++ 4 files changed, 866 insertions(+) create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-narrowing-fixed-point-clip/thead/vnclip.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-narrowing-fixed-point-clip/thead/vnclipu.c diff --git a/clang/include/clang/Basic/riscv_vector_xtheadv.td b/clang/include/clang/Basic/riscv_vector_xtheadv.td index 4c06f76a1d8ff..1bd8480b58134 100644 --- a/clang/include/clang/Basic/riscv_vector_xtheadv.td +++ b/clang/include/clang/Basic/riscv_vector_xtheadv.td @@ -1041,5 +1041,53 @@ let UnMaskedPolicyScheme = HasPassthruOperand, defm th_vsmul : RVVSignedBinBuiltinSetRoundingMode; } +// 13.5 Vector Narrowing Fixed-Point Clip Operations +let UnMaskedPolicyScheme = HasPassthruOperand, + MaskedPolicyScheme = HasPassthruOperand, + ManualCodegen = [{ + { + // LLVM intrinsic + // Unmasked: (passthru, op0, op1, vxrm, vl) + // Masked: (passthru, vector_in, vector_in/scalar_in, mask, vxrm, vl) + + // Clang builtin + // Unmask: (op1, op2, vxrm, vl) + // Mask: (mask, op1, op2, vxrm, vl) + + SmallVector Operands; + bool HasMaskedOff = !( + (IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) || + (!IsMasked && PolicyAttrs & RVV_VTA)); + unsigned Offset = IsMasked ? + (HasMaskedOff ? 2 : 1) : (HasMaskedOff ? 1 : 0); + + if (!HasMaskedOff) + Operands.push_back(llvm::PoisonValue::get(ResultType)); + else + Operands.push_back(Ops[IsMasked ? 1 : 0]); + + Operands.push_back(Ops[Offset]); // op0 + Operands.push_back(Ops[Offset + 1]); // op1 + + if (IsMasked) + Operands.push_back(Ops[0]); // mask + + Operands.push_back(Ops[Offset + 2]); // vxrm + Operands.push_back(Ops[Offset + 3]); // vl + + // TODO: no policy in LLVM side for masked intrinsics. + // if (IsMasked) + // Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs)); + + IntrinsicTypes = {ResultType, Ops[Offset]->getType(), Ops[Offset + 1]->getType(), + Ops.back()->getType()}; + llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); + return Builder.CreateCall(F, Operands, ""); + } +}] in { + // 13.5. Vector Narrowing Fixed-Point Clip Instructions + defm th_vnclipu : RVVUnsignedNShiftBuiltinSetRoundingMode; + defm th_vnclip : RVVSignedNShiftBuiltinSetRoundingMode; +} include "riscv_vector_xtheadv_wrappers.td" diff --git a/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td b/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td index 9a2d547002ced..4ffda72626d26 100644 --- a/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td +++ b/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td @@ -2189,3 +2189,87 @@ let HeaderCode = }] in def th_single_width_fractional_multiply_with_rounding_and_saturation_wrapper_macros: RVVHeader; + +// 13.5. Vector Narrowing Fixed-Point Clip Operations + +let HeaderCode = +[{ +// Vector Narrowing Fixed-Point Clip Operations +#define __riscv_vnclip_wv_i8m1(op1, op2, rm, vl) __riscv_th_vnclip_wv_i8m1(op1, op2, rm, vl) +#define __riscv_vnclip_wx_i8m1(op1, op2, rm, vl) __riscv_th_vnclip_wx_i8m1(op1, op2, rm, vl) +#define __riscv_vnclip_wv_i8m2(op1, op2, rm, vl) __riscv_th_vnclip_wv_i8m2(op1, op2, rm, vl) +#define __riscv_vnclip_wx_i8m2(op1, op2, rm, vl) __riscv_th_vnclip_wx_i8m2(op1, op2, rm, vl) +#define __riscv_vnclip_wv_i8m4(op1, op2, rm, vl) __riscv_th_vnclip_wv_i8m4(op1, op2, rm, vl) +#define __riscv_vnclip_wx_i8m4(op1, op2, rm, vl) __riscv_th_vnclip_wx_i8m4(op1, op2, rm, vl) +#define __riscv_vnclip_wv_i16m1(op1, op2, rm, vl) __riscv_th_vnclip_wv_i16m1(op1, op2, rm, vl) +#define __riscv_vnclip_wx_i16m1(op1, op2, rm, vl) __riscv_th_vnclip_wx_i16m1(op1, op2, rm, vl) +#define __riscv_vnclip_wv_i16m2(op1, op2, rm, vl) __riscv_th_vnclip_wv_i16m2(op1, op2, rm, vl) +#define __riscv_vnclip_wx_i16m2(op1, op2, rm, vl) __riscv_th_vnclip_wx_i16m2(op1, op2, rm, vl) +#define __riscv_vnclip_wv_i16m4(op1, op2, rm, vl) __riscv_th_vnclip_wv_i16m4(op1, op2, rm, vl) +#define __riscv_vnclip_wx_i16m4(op1, op2, rm, vl) __riscv_th_vnclip_wx_i16m4(op1, op2, rm, vl) +#define __riscv_vnclip_wv_i32m1(op1, op2, rm, vl) __riscv_th_vnclip_wv_i32m1(op1, op2, rm, vl) +#define __riscv_vnclip_wx_i32m1(op1, op2, rm, vl) __riscv_th_vnclip_wx_i32m1(op1, op2, rm, vl) +#define __riscv_vnclip_wv_i32m2(op1, op2, rm, vl) __riscv_th_vnclip_wv_i32m2(op1, op2, rm, vl) +#define __riscv_vnclip_wx_i32m2(op1, op2, rm, vl) __riscv_th_vnclip_wx_i32m2(op1, op2, rm, vl) +#define __riscv_vnclip_wv_i32m4(op1, op2, rm, vl) __riscv_th_vnclip_wv_i32m4(op1, op2, rm, vl) +#define __riscv_vnclip_wx_i32m4(op1, op2, rm, vl) __riscv_th_vnclip_wx_i32m4(op1, op2, rm, vl) + +#define __riscv_vnclip_wv_i8m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wv_i8m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wx_i8m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wx_i8m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wv_i8m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wv_i8m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wx_i8m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wx_i8m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wv_i8m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wv_i8m4_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wx_i8m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wx_i8m4_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wv_i16m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wv_i16m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wx_i16m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wx_i16m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wv_i16m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wv_i16m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wx_i16m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wx_i16m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wv_i16m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wv_i16m4_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wx_i16m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wx_i16m4_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wv_i32m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wv_i32m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wx_i32m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wx_i32m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wv_i32m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wv_i32m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wx_i32m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wx_i32m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wv_i32m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wv_i32m4_m(mask, op1, op2, rm, vl) +#define __riscv_vnclip_wx_i32m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclip_wx_i32m4_m(mask, op1, op2, rm, vl) + +#define __riscv_vnclipu_wv_u8m1(op1, op2, rm, vl) __riscv_th_vnclipu_wv_u8m1(op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u8m1(op1, op2, rm, vl) __riscv_th_vnclipu_wx_u8m1(op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u8m2(op1, op2, rm, vl) __riscv_th_vnclipu_wv_u8m2(op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u8m2(op1, op2, rm, vl) __riscv_th_vnclipu_wx_u8m2(op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u8m4(op1, op2, rm, vl) __riscv_th_vnclipu_wv_u8m4(op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u8m4(op1, op2, rm, vl) __riscv_th_vnclipu_wx_u8m4(op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u16m1(op1, op2, rm, vl) __riscv_th_vnclipu_wv_u16m1(op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u16m1(op1, op2, rm, vl) __riscv_th_vnclipu_wx_u16m1(op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u16m2(op1, op2, rm, vl) __riscv_th_vnclipu_wv_u16m2(op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u16m2(op1, op2, rm, vl) __riscv_th_vnclipu_wx_u16m2(op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u16m4(op1, op2, rm, vl) __riscv_th_vnclipu_wv_u16m4(op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u16m4(op1, op2, rm, vl) __riscv_th_vnclipu_wx_u16m4(op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u32m1(op1, op2, rm, vl) __riscv_th_vnclipu_wv_u32m1(op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u32m1(op1, op2, rm, vl) __riscv_th_vnclipu_wx_u32m1(op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u32m2(op1, op2, rm, vl) __riscv_th_vnclipu_wv_u32m2(op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u32m2(op1, op2, rm, vl) __riscv_th_vnclipu_wx_u32m2(op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u32m4(op1, op2, rm, vl) __riscv_th_vnclipu_wv_u32m4(op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u32m4(op1, op2, rm, vl) __riscv_th_vnclipu_wx_u32m4(op1, op2, rm, vl) + +#define __riscv_vnclipu_wv_u8m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wv_u8m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u8m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wx_u8m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u8m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wv_u8m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u8m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wx_u8m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u8m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wv_u8m4_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u8m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wx_u8m4_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u16m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wv_u16m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u16m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wx_u16m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u16m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wv_u16m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u16m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wx_u16m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u16m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wv_u16m4_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u16m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wx_u16m4_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u32m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wv_u32m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u32m1_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wx_u32m1_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u32m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wv_u32m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u32m2_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wx_u32m2_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wv_u32m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wv_u32m4_m(mask, op1, op2, rm, vl) +#define __riscv_vnclipu_wx_u32m4_m(mask, op1, op2, rm, vl) __riscv_th_vnclipu_wx_u32m4_m(mask, op1, op2, rm, vl) + +}] in +def th_narrowing_width_fixed_point_clip_wrapper_macros: RVVHeader; diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-narrowing-fixed-point-clip/thead/vnclip.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-narrowing-fixed-point-clip/thead/vnclip.c new file mode 100644 index 0000000000000..548ce86a9c20b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-narrowing-fixed-point-clip/thead/vnclip.c @@ -0,0 +1,367 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i8m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vnclip_wv_i8m1(vint16m2_t op1, vuint8m1_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i8m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i8m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv8i8.nxv8i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vnclip_wx_i8m1(vint16m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i8m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i8m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv16i8.nxv16i16.nxv16i8.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vnclip_wv_i8m2(vint16m4_t op1, vuint8m2_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i8m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i8m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv16i8.nxv16i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vnclip_wx_i8m2(vint16m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i8m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i8m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv32i8.nxv32i16.nxv32i8.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vnclip_wv_i8m4(vint16m8_t op1, vuint8m4_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i8m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i8m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv32i8.nxv32i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vnclip_wx_i8m4(vint16m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i8m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i16m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv4i16.nxv4i32.nxv4i16.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vnclip_wv_i16m1(vint32m2_t op1, vuint16m1_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i16m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i16m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv4i16.nxv4i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vnclip_wx_i16m1(vint32m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i16m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i16m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv8i16.nxv8i32.nxv8i16.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vnclip_wv_i16m2(vint32m4_t op1, vuint16m2_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i16m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i16m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv8i16.nxv8i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vnclip_wx_i16m2(vint32m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i16m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i16m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv16i16.nxv16i32.nxv16i16.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vnclip_wv_i16m4(vint32m8_t op1, vuint16m4_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i16m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i16m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv16i16.nxv16i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vnclip_wx_i16m4(vint32m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i16m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i32m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv2i32.nxv2i64.nxv2i32.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vnclip_wv_i32m1(vint64m2_t op1, vuint32m1_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i32m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i32m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv2i32.nxv2i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vnclip_wx_i32m1(vint64m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i32m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i32m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv4i32.nxv4i64.nxv4i32.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vnclip_wv_i32m2(vint64m4_t op1, vuint32m2_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i32m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i32m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv4i32.nxv4i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vnclip_wx_i32m2(vint64m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i32m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i32m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv8i32.nxv8i64.nxv8i32.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vnclip_wv_i32m4(vint64m8_t op1, vuint32m4_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i32m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i32m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.nxv8i32.nxv8i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vnclip_wx_i32m4(vint64m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i32m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i8m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv8i8.nxv8i16.nxv8i8.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vnclip_wv_i8m1_m(vbool8_t mask, vint16m2_t op1, vuint8m1_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i8m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i8m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv8i8.nxv8i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vnclip_wx_i8m1_m(vbool8_t mask, vint16m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i8m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i8m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv16i8.nxv16i16.nxv16i8.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vnclip_wv_i8m2_m(vbool4_t mask, vint16m4_t op1, vuint8m2_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i8m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i8m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv16i8.nxv16i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vnclip_wx_i8m2_m(vbool4_t mask, vint16m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i8m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i8m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv32i8.nxv32i16.nxv32i8.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vnclip_wv_i8m4_m(vbool2_t mask, vint16m8_t op1, vuint8m4_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i8m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i8m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv32i8.nxv32i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vnclip_wx_i8m4_m(vbool2_t mask, vint16m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i8m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv4i16.nxv4i32.nxv4i16.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vnclip_wv_i16m1_m(vbool16_t mask, vint32m2_t op1, vuint16m1_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i16m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv4i16.nxv4i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vnclip_wx_i16m1_m(vbool16_t mask, vint32m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i16m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv8i16.nxv8i32.nxv8i16.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vnclip_wv_i16m2_m(vbool8_t mask, vint32m4_t op1, vuint16m2_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i16m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv8i16.nxv8i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vnclip_wx_i16m2_m(vbool8_t mask, vint32m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i16m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv16i16.nxv16i32.nxv16i16.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vnclip_wv_i16m4_m(vbool4_t mask, vint32m8_t op1, vuint16m4_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i16m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv16i16.nxv16i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vnclip_wx_i16m4_m(vbool4_t mask, vint32m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i16m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv2i32.nxv2i64.nxv2i32.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vnclip_wv_i32m1_m(vbool32_t mask, vint64m2_t op1, vuint32m1_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i32m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv2i32.nxv2i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vnclip_wx_i32m1_m(vbool32_t mask, vint64m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i32m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv4i32.nxv4i64.nxv4i32.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vnclip_wv_i32m2_m(vbool16_t mask, vint64m4_t op1, vuint32m2_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i32m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv4i32.nxv4i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vnclip_wx_i32m2_m(vbool16_t mask, vint64m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i32m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wv_i32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv8i32.nxv8i64.nxv8i32.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vnclip_wv_i32m4_m(vbool8_t mask, vint64m8_t op1, vuint32m4_t shift, size_t vl) { + return __riscv_th_vnclip_wv_i32m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclip_wx_i32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclip.mask.nxv8i32.nxv8i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vnclip_wx_i32m4_m(vbool8_t mask, vint64m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclip_wx_i32m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-narrowing-fixed-point-clip/thead/vnclipu.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-narrowing-fixed-point-clip/thead/vnclipu.c new file mode 100644 index 0000000000000..9dedef37b53f9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-narrowing-fixed-point-clip/thead/vnclipu.c @@ -0,0 +1,367 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u8m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vnclipu_wv_u8m1(vuint16m2_t op1, vuint8m1_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u8m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u8m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv8i8.nxv8i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vnclipu_wx_u8m1(vuint16m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u8m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u8m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vnclipu_wv_u8m2(vuint16m4_t op1, vuint8m2_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u8m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u8m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv16i8.nxv16i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vnclipu_wx_u8m2(vuint16m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u8m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u8m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv32i8.nxv32i16.nxv32i8.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vnclipu_wv_u8m4(vuint16m8_t op1, vuint8m4_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u8m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u8m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv32i8.nxv32i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vnclipu_wx_u8m4(vuint16m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u8m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u16m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv4i16.nxv4i32.nxv4i16.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vnclipu_wv_u16m1(vuint32m2_t op1, vuint16m1_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u16m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u16m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv4i16.nxv4i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vnclipu_wx_u16m1(vuint32m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u16m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u16m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv8i16.nxv8i32.nxv8i16.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vnclipu_wv_u16m2(vuint32m4_t op1, vuint16m2_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u16m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u16m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv8i16.nxv8i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vnclipu_wx_u16m2(vuint32m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u16m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u16m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv16i16.nxv16i32.nxv16i16.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vnclipu_wv_u16m4(vuint32m8_t op1, vuint16m4_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u16m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u16m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv16i16.nxv16i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vnclipu_wx_u16m4(vuint32m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u16m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u32m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv2i32.nxv2i64.nxv2i32.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vnclipu_wv_u32m1(vuint64m2_t op1, vuint32m1_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u32m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u32m1 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv2i32.nxv2i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vnclipu_wx_u32m1(vuint64m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u32m1(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u32m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv4i32.nxv4i64.nxv4i32.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vnclipu_wv_u32m2(vuint64m4_t op1, vuint32m2_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u32m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u32m2 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv4i32.nxv4i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vnclipu_wx_u32m2(vuint64m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u32m2(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u32m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv8i32.nxv8i64.nxv8i32.i64( poison, [[OP1]], [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vnclipu_wv_u32m4(vuint64m8_t op1, vuint32m4_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u32m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u32m4 +// CHECK-RV64-SAME: ( [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.nxv8i32.nxv8i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vnclipu_wx_u32m4(vuint64m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u32m4(op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u8m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv8i8.nxv8i16.nxv8i8.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vnclipu_wv_u8m1_m(vbool8_t mask, vuint16m2_t op1, vuint8m1_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u8m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u8m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv8i8.nxv8i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vnclipu_wx_u8m1_m(vbool8_t mask, vuint16m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u8m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u8m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv16i8.nxv16i16.nxv16i8.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vnclipu_wv_u8m2_m(vbool4_t mask, vuint16m4_t op1, vuint8m2_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u8m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u8m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv16i8.nxv16i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vnclipu_wx_u8m2_m(vbool4_t mask, vuint16m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u8m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u8m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv32i8.nxv32i16.nxv32i8.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vnclipu_wv_u8m4_m(vbool2_t mask, vuint16m8_t op1, vuint8m4_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u8m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u8m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv32i8.nxv32i16.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vnclipu_wx_u8m4_m(vbool2_t mask, vuint16m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u8m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv4i16.nxv4i32.nxv4i16.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vnclipu_wv_u16m1_m(vbool16_t mask, vuint32m2_t op1, vuint16m1_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u16m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv4i16.nxv4i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vnclipu_wx_u16m1_m(vbool16_t mask, vuint32m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u16m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv8i16.nxv8i32.nxv8i16.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vnclipu_wv_u16m2_m(vbool8_t mask, vuint32m4_t op1, vuint16m2_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u16m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv8i16.nxv8i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vnclipu_wx_u16m2_m(vbool8_t mask, vuint32m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u16m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv16i16.nxv16i32.nxv16i16.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vnclipu_wv_u16m4_m(vbool4_t mask, vuint32m8_t op1, vuint16m4_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u16m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv16i16.nxv16i32.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vnclipu_wx_u16m4_m(vbool4_t mask, vuint32m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u16m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv2i32.nxv2i64.nxv2i32.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vnclipu_wv_u32m1_m(vbool32_t mask, vuint64m2_t op1, vuint32m1_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u32m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv2i32.nxv2i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vnclipu_wx_u32m1_m(vbool32_t mask, vuint64m2_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u32m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv4i32.nxv4i64.nxv4i32.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vnclipu_wv_u32m2_m(vbool16_t mask, vuint64m4_t op1, vuint32m2_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u32m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv4i32.nxv4i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vnclipu_wx_u32m2_m(vbool16_t mask, vuint64m4_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u32m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wv_u32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv8i32.nxv8i64.nxv8i32.i64( poison, [[OP1]], [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vnclipu_wv_u32m4_m(vbool8_t mask, vuint64m8_t op1, vuint32m4_t shift, size_t vl) { + return __riscv_th_vnclipu_wv_u32m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vnclipu_wx_u32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vnclipu.mask.nxv8i32.nxv8i64.i64.i64( poison, [[OP1]], i64 [[SHIFT]], [[MASK]], i64 0, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vnclipu_wx_u32m4_m(vbool8_t mask, vuint64m8_t op1, size_t shift, size_t vl) { + return __riscv_th_vnclipu_wx_u32m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl); +} +