diff --git a/Makefile b/Makefile
index 0f4ddb1..35a9cde 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
-#yosys_cmd   = yosys -p 'read_verilog +/xilinx/cells_xtra.v $(1)/*.v; synth_xilinx -edif $(1).edif -top $(1)'
-yosys_cmd   = yosys -p 'read_verilog $(1)/*.v; synth_xilinx -edif $(1).edif -top $(1)'
+yosys_cmd   = yosys -p 'read_verilog +/xilinx/cells_xtra.v $(1)/*.v; synth_xilinx -edif $(1).edif -top $(1)'
+#yosys_cmd   = yosys -p 'read_verilog $(1)/*.v; synth_xilinx -edif $(1).edif -top $(1)'
 vivado_cmd  = vivado -nolog -nojournal -mode batch -source $(1).tcl
 vivado_tcl  = echo -e "read_xdc pynq.xdc\n\
 	     read_edif $(1).edif\n\
diff --git a/blink/blink.v b/blink/blink.v
index 8ccee68..bbdee7c 100644
--- a/blink/blink.v
+++ b/blink/blink.v
@@ -1,11 +1,11 @@
 module blink (
-	input	clk,
 	output	[3:0]led
 );
 
+	wire [3:0] fclk;
 	reg status;
 
-	always @(posedge clk) begin
+	always @(posedge fclk[0]) begin
 		if (status == 0)
 			status <= 1;
 		else
@@ -16,6 +16,10 @@ module blink (
 	assign led[1] = status;
 	assign led[2] = status;
 	assign led[3] = status;
+
+	PS7 the_PS (
+		.FCLKCLK (fclk)
+	);
 endmodule
 
 
diff --git a/pynq.xdc b/pynq.xdc
index 64c830a..afd6e42 100644
--- a/pynq.xdc
+++ b/pynq.xdc
@@ -1,4 +1,4 @@
-set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk]
+#set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk]
 
 set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports led[0]]
 set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports led[1]]