TLAST Signal Missing in IP Core Generated by HLS4ML

[SIRIDHARI]

Hi,
I am using Vitis HLS for my signature forgery detection project. I wrote the ML model in Python and used HLS4ML to convert it into C++ files. I then used Vitis HLS to generate RTL files.

I am planning to include DMA in my block design, so I need the TLAST signal. However, although I am using io_stream in HLS4ML (which should automatically generate the TLAST signal), it is not being generated in the RTL files.

Additionally, I am unsure where to connect the ap_ctrl signals generated in the IP core within the Vivado block design.

Has anyone faced a similar issue or knows how to ensure TLAST is included in the RTL design? Any help or suggestions would be greatly appreciated.

[bo3z]

What version of Vitis HLS are you using? As far as I am aware, tlast should always be part of the AXI stream specification, but it might be a bug in the specific version of HLS.

It could have also been optimized away - Vitis HLS might notice that the kernel is not connected to a larger design and conclude TLAST is not needed; though this to me seems unlikely to happen at Vitis HLS synth time; it should really happen at Vivado synthesis. But you can inspect the vitis_hls.log file for occurences of last or tlast.

ap_ctrl is for control signals from the host. Whether you use it or not depends on how your HLS kernel is started? Does it start "internaly" whenever it gets all the data it needs or does it need some explicit control signal to start. You can tweak the #pragma HLS INTERFACE in the myproject.cpp to fit your application.