Error in code synthesys

[andresfbt]

I am trying to create a CNN for the mnist dataset. The code is basically copy-pasted from the tutorial 6, changing the dataset to the mnist dataset, and my fpga part. The process, however fails in the synthesis. It seems Vitis or Vivado fails to detect/create one of the ips (myproject_fpext_32ns_64_2_no_dsp_1_ip). The myproject_fpext_32ns_64_2_no_dsp_1_ip.tcl file is in the same folder as the myproject_fpext_32ns_64_2_no_dsp_1.v file. Does anyone know what could be causing this issue, or a possible fix?

This is the relevant part of the log, I will attach the rest as a text file.
error.txt

INFO: [Synth 8-6157] synthesizing module 'myproject_fpext_32ns_64_2_no_dsp_1' [/home/pelao/Documents/hls4ml/cnn_mnist_tut6/model_1/hls4ml_prj/myproject_prj/solution1/syn/verilog/myproject_fpext_32ns_64_2_no_dsp_1.v:9]
Parameter ID bound to: 1 - type: integer
Parameter NUM_STAGE bound to: 2 - type: integer
Parameter din0_WIDTH bound to: 32 - type: integer
Parameter dout_WIDTH bound to: 64 - type: integer

Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1941.281 ; gain = 644.715 ; free physical = 606 ; free virtual = 59949

synthesize failed
INFO: [Common 17-83] Releasing license: Synthesis
175 Infos, 0 Warnings, 0 Critical Warnings and 7 Errors encountered.
synth_design failed
INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 00:09:18 2025...
ERROR: [Synth 8-439] module 'myproject_fpext_32ns_64_2_no_dsp_1_ip' not found [/home/pelao/Documents/hls4ml/cnn_mnist_tut6/model_1/hls4ml_prj/myproject_prj/solution1/syn/verilog/myproject_fpext_32ns_64_2_no_dsp_1.v:32]
ERROR: [Synth 8-6156] failed synthesizing module 'myproject_fpext_32ns_64_2_no_dsp_1' [/home/pelao/Documents/hls4ml/cnn_mnist_tut6/model_1/hls4ml_prj/myproject_prj/solution1/syn/verilog/myproject_fpext_32ns_64_2_no_dsp_1.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'myproject_init_exp_table_ap_fixed_39_19_5_3_0_softmax_config28_s' [/home/pelao/Documents/hls4ml/cnn_mnist_tut6/model_1/hls4ml_prj/myproject_prj/solution1/syn/verilog/myproject_init_exp_table_ap_fixed_39_19_5_3_0_softmax_config28_s.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'myproject_softmax_stable_array_array_ap_fixed_16_6_5_3_0_10u_softmax_config28_s' [/home/pelao/Documents/hls4ml/cnn_mnist_tut6/model_1/hls4ml_prj/myproject_prj/solution1/syn/verilog/myproject_softmax_stable_array_array_ap_fixed_16_6_5_3_0_10u_softmax_config28_s.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'myproject_softmax_array_array_ap_fixed_16_6_5_3_0_10u_softmax_config28_s' [/home/pelao/Documents/hls4ml/cnn_mnist_tut6/model_1/hls4ml_prj/myproject_prj/solution1/syn/verilog/myproject_softmax_array_array_ap_fixed_16_6_5_3_0_10u_softmax_config28_s.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'myproject' [/home/pelao/Documents/hls4ml/cnn_mnist_tut6/model_1/hls4ml_prj/myproject_prj/solution1/syn/verilog/myproject.v:9]
ERROR: [Common 17-69] Command failed: Vivado Synthesis failed
while executing
"exec vivado -mode batch -source vivado_synth.tcl >@ stdout"
invoked from within
"if {$opt(vsynth)} {
puts "***** VIVADO SYNTHESIS *****"
if {[file exist ${project_name}_prj/solution1/syn/verilog]} {
set time_start [..."
(file "build_prj.tcl" line 237)
invoked from within
"source build_prj.tcl"
("uplevel" body line 1)
invoked from within
"uplevel #0 [list source $arg] "

INFO: [HLS 200-112] Total CPU user time: 310.25 seconds. Total CPU system time: 6.09 seconds. Total elapsed time: 326.26 seconds; peak allocated memory: 2.159 GB.

[bo3z]

Make sure to reset your HLS project when running the synthesis (or better yet, delete the myproject_prj folder fully and then re-run HLS synthesis). This kind of error typically occurs when some files generated by HLS haven't beed added to the project (because the project thinks it doesn't need them, due to some previous checkpoint).

[andresfbt]

I tried deleting the files and running with different vitis versions, but the error persists. I also tried running the tutorial 6 as is, and I got the same error. Could it be possible to manually add the files from a previously synthetized project?

[bo3z]

Could you provide the script and environment details (vivado version, OS etc.) that causes this error, especially how you trigger the synthesis? The HLS project should always include all of its files, unless some files have been manually added to the project, so it's a bit hard to say what went wrong.