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kwbimage.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Image manipulator for Marvell SoCs
* supports Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and
* Armada 39x
*
* (C) Copyright 2013 Thomas Petazzoni
*
* (C) Copyright 2022 Pali Rohár <[email protected]>
*/
#define OPENSSL_API_COMPAT 0x10101000L
#include "imagetool.h"
#include <limits.h>
#include <image.h>
#include <stdarg.h>
#include <stdint.h>
#include "kwbimage.h"
#include <openssl/bn.h>
#include <openssl/rsa.h>
#include <openssl/pem.h>
#include <openssl/err.h>
#include <openssl/evp.h>
#if OPENSSL_VERSION_NUMBER < 0x10100000L || \
(defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x2070000fL)
static void RSA_get0_key(const RSA *r,
const BIGNUM **n, const BIGNUM **e, const BIGNUM **d)
{
if (n != NULL)
*n = r->n;
if (e != NULL)
*e = r->e;
if (d != NULL)
*d = r->d;
}
#elif !defined(LIBRESSL_VERSION_NUMBER)
void EVP_MD_CTX_cleanup(EVP_MD_CTX *ctx)
{
EVP_MD_CTX_reset(ctx);
}
#endif
/* fls - find last (most-significant) bit set in 4-bit integer */
static inline int fls4(int num)
{
if (num & 0x8)
return 4;
else if (num & 0x4)
return 3;
else if (num & 0x2)
return 2;
else if (num & 0x1)
return 1;
else
return 0;
}
static struct image_cfg_element *image_cfg;
static int cfgn;
static int verbose_mode;
struct boot_mode {
unsigned int id;
const char *name;
};
/*
* SHA2-256 hash
*/
struct hash_v1 {
uint8_t hash[32];
};
struct boot_mode boot_modes[] = {
{ IBR_HDR_I2C_ID, "i2c" },
{ IBR_HDR_SPI_ID, "spi" },
{ IBR_HDR_NAND_ID, "nand" },
{ IBR_HDR_SATA_ID, "sata" },
{ IBR_HDR_PEX_ID, "pex" },
{ IBR_HDR_UART_ID, "uart" },
{ IBR_HDR_SDIO_ID, "sdio" },
{},
};
struct nand_ecc_mode {
unsigned int id;
const char *name;
};
struct nand_ecc_mode nand_ecc_modes[] = {
{ IBR_HDR_ECC_DEFAULT, "default" },
{ IBR_HDR_ECC_FORCED_HAMMING, "hamming" },
{ IBR_HDR_ECC_FORCED_RS, "rs" },
{ IBR_HDR_ECC_DISABLED, "disabled" },
{},
};
/* Used to identify an undefined execution or destination address */
#define ADDR_INVALID ((uint32_t)-1)
#define BINARY_MAX_ARGS 255
/* In-memory representation of a line of the configuration file */
enum image_cfg_type {
IMAGE_CFG_VERSION = 0x1,
IMAGE_CFG_BOOT_FROM,
IMAGE_CFG_DEST_ADDR,
IMAGE_CFG_EXEC_ADDR,
IMAGE_CFG_NAND_BLKSZ,
IMAGE_CFG_NAND_BADBLK_LOCATION,
IMAGE_CFG_NAND_ECC_MODE,
IMAGE_CFG_NAND_PAGESZ,
IMAGE_CFG_CPU,
IMAGE_CFG_BINARY,
IMAGE_CFG_DATA,
IMAGE_CFG_DATA_DELAY,
IMAGE_CFG_BAUDRATE,
IMAGE_CFG_UART_PORT,
IMAGE_CFG_UART_MPP,
IMAGE_CFG_DEBUG,
IMAGE_CFG_KAK,
IMAGE_CFG_CSK,
IMAGE_CFG_CSK_INDEX,
IMAGE_CFG_JTAG_DELAY,
IMAGE_CFG_BOX_ID,
IMAGE_CFG_FLASH_ID,
IMAGE_CFG_SEC_COMMON_IMG,
IMAGE_CFG_SEC_SPECIALIZED_IMG,
IMAGE_CFG_SEC_BOOT_DEV,
IMAGE_CFG_SEC_FUSE_DUMP,
IMAGE_CFG_COUNT
} type;
static const char * const id_strs[] = {
[IMAGE_CFG_VERSION] = "VERSION",
[IMAGE_CFG_BOOT_FROM] = "BOOT_FROM",
[IMAGE_CFG_DEST_ADDR] = "DEST_ADDR",
[IMAGE_CFG_EXEC_ADDR] = "EXEC_ADDR",
[IMAGE_CFG_NAND_BLKSZ] = "NAND_BLKSZ",
[IMAGE_CFG_NAND_BADBLK_LOCATION] = "NAND_BADBLK_LOCATION",
[IMAGE_CFG_NAND_ECC_MODE] = "NAND_ECC_MODE",
[IMAGE_CFG_NAND_PAGESZ] = "NAND_PAGE_SIZE",
[IMAGE_CFG_CPU] = "CPU",
[IMAGE_CFG_BINARY] = "BINARY",
[IMAGE_CFG_DATA] = "DATA",
[IMAGE_CFG_DATA_DELAY] = "DATA_DELAY",
[IMAGE_CFG_BAUDRATE] = "BAUDRATE",
[IMAGE_CFG_UART_PORT] = "UART_PORT",
[IMAGE_CFG_UART_MPP] = "UART_MPP",
[IMAGE_CFG_DEBUG] = "DEBUG",
[IMAGE_CFG_KAK] = "KAK",
[IMAGE_CFG_CSK] = "CSK",
[IMAGE_CFG_CSK_INDEX] = "CSK_INDEX",
[IMAGE_CFG_JTAG_DELAY] = "JTAG_DELAY",
[IMAGE_CFG_BOX_ID] = "BOX_ID",
[IMAGE_CFG_FLASH_ID] = "FLASH_ID",
[IMAGE_CFG_SEC_COMMON_IMG] = "SEC_COMMON_IMG",
[IMAGE_CFG_SEC_SPECIALIZED_IMG] = "SEC_SPECIALIZED_IMG",
[IMAGE_CFG_SEC_BOOT_DEV] = "SEC_BOOT_DEV",
[IMAGE_CFG_SEC_FUSE_DUMP] = "SEC_FUSE_DUMP"
};
struct image_cfg_element {
enum image_cfg_type type;
union {
unsigned int version;
unsigned int cpu_sheeva;
unsigned int bootfrom;
struct {
const char *file;
unsigned int loadaddr;
unsigned int args[BINARY_MAX_ARGS];
unsigned int nargs;
} binary;
unsigned int dstaddr;
unsigned int execaddr;
unsigned int nandblksz;
unsigned int nandbadblklocation;
unsigned int nandeccmode;
unsigned int nandpagesz;
struct ext_hdr_v0_reg regdata;
unsigned int regdata_delay;
unsigned int baudrate;
unsigned int uart_port;
unsigned int uart_mpp;
unsigned int debug;
const char *key_name;
int csk_idx;
uint8_t jtag_delay;
uint32_t boxid;
uint32_t flashid;
bool sec_specialized_img;
unsigned int sec_boot_dev;
const char *name;
};
};
#define IMAGE_CFG_ELEMENT_MAX 256
/*
* Utility functions to manipulate boot mode and ecc modes (convert
* them back and forth between description strings and the
* corresponding numerical identifiers).
*/
static const char *image_boot_mode_name(unsigned int id)
{
int i;
for (i = 0; boot_modes[i].name; i++)
if (boot_modes[i].id == id)
return boot_modes[i].name;
return NULL;
}
static int image_boot_mode_id(const char *boot_mode_name)
{
int i;
for (i = 0; boot_modes[i].name; i++)
if (!strcmp(boot_modes[i].name, boot_mode_name))
return boot_modes[i].id;
return -1;
}
static const char *image_nand_ecc_mode_name(unsigned int id)
{
int i;
for (i = 0; nand_ecc_modes[i].name; i++)
if (nand_ecc_modes[i].id == id)
return nand_ecc_modes[i].name;
return NULL;
}
static int image_nand_ecc_mode_id(const char *nand_ecc_mode_name)
{
int i;
for (i = 0; nand_ecc_modes[i].name; i++)
if (!strcmp(nand_ecc_modes[i].name, nand_ecc_mode_name))
return nand_ecc_modes[i].id;
return -1;
}
static struct image_cfg_element *
image_find_option(unsigned int optiontype)
{
int i;
for (i = 0; i < cfgn; i++) {
if (image_cfg[i].type == optiontype)
return &image_cfg[i];
}
return NULL;
}
static unsigned int
image_count_options(unsigned int optiontype)
{
int i;
unsigned int count = 0;
for (i = 0; i < cfgn; i++)
if (image_cfg[i].type == optiontype)
count++;
return count;
}
static int image_get_csk_index(void)
{
struct image_cfg_element *e;
e = image_find_option(IMAGE_CFG_CSK_INDEX);
if (!e)
return -1;
return e->csk_idx;
}
static bool image_get_spezialized_img(void)
{
struct image_cfg_element *e;
e = image_find_option(IMAGE_CFG_SEC_SPECIALIZED_IMG);
if (!e)
return false;
return e->sec_specialized_img;
}
static int image_get_bootfrom(void)
{
struct image_cfg_element *e;
e = image_find_option(IMAGE_CFG_BOOT_FROM);
if (!e)
/* fallback to SPI if no BOOT_FROM is not provided */
return IBR_HDR_SPI_ID;
return e->bootfrom;
}
static int image_is_cpu_sheeva(void)
{
struct image_cfg_element *e;
e = image_find_option(IMAGE_CFG_CPU);
if (!e)
return 0;
return e->cpu_sheeva;
}
/*
* Compute a 8-bit checksum of a memory area. This algorithm follows
* the requirements of the Marvell SoC BootROM specifications.
*/
static uint8_t image_checksum8(void *start, uint32_t len)
{
uint8_t csum = 0;
uint8_t *p = start;
/* check len and return zero checksum if invalid */
if (!len)
return 0;
do {
csum += *p;
p++;
} while (--len);
return csum;
}
/*
* Verify checksum over a complete header that includes the checksum field.
* Return 1 when OK, otherwise 0.
*/
static int main_hdr_checksum_ok(void *hdr)
{
/* Offsets of checksum in v0 and v1 headers are the same */
struct main_hdr_v0 *main_hdr = (struct main_hdr_v0 *)hdr;
uint8_t checksum;
checksum = image_checksum8(hdr, kwbheader_size_for_csum(hdr));
/* Calculated checksum includes the header checksum field. Compensate
* for that.
*/
checksum -= main_hdr->checksum;
return checksum == main_hdr->checksum;
}
static uint32_t image_checksum32(void *start, uint32_t len)
{
uint32_t csum = 0;
uint32_t *p = start;
/* check len and return zero checksum if invalid */
if (!len)
return 0;
if (len % sizeof(uint32_t)) {
fprintf(stderr, "Length %d is not in multiple of %zu\n",
len, sizeof(uint32_t));
return 0;
}
do {
csum += *p;
p++;
len -= sizeof(uint32_t);
} while (len > 0);
return csum;
}
static unsigned int options_to_baudrate(uint8_t options)
{
switch (options & 0x7) {
case MAIN_HDR_V1_OPT_BAUD_2400:
return 2400;
case MAIN_HDR_V1_OPT_BAUD_4800:
return 4800;
case MAIN_HDR_V1_OPT_BAUD_9600:
return 9600;
case MAIN_HDR_V1_OPT_BAUD_19200:
return 19200;
case MAIN_HDR_V1_OPT_BAUD_38400:
return 38400;
case MAIN_HDR_V1_OPT_BAUD_57600:
return 57600;
case MAIN_HDR_V1_OPT_BAUD_115200:
return 115200;
case MAIN_HDR_V1_OPT_BAUD_DEFAULT:
default:
return 0;
}
}
static uint8_t baudrate_to_option(unsigned int baudrate)
{
switch (baudrate) {
case 2400:
return MAIN_HDR_V1_OPT_BAUD_2400;
case 4800:
return MAIN_HDR_V1_OPT_BAUD_4800;
case 9600:
return MAIN_HDR_V1_OPT_BAUD_9600;
case 19200:
return MAIN_HDR_V1_OPT_BAUD_19200;
case 38400:
return MAIN_HDR_V1_OPT_BAUD_38400;
case 57600:
return MAIN_HDR_V1_OPT_BAUD_57600;
case 115200:
return MAIN_HDR_V1_OPT_BAUD_115200;
default:
return MAIN_HDR_V1_OPT_BAUD_DEFAULT;
}
}
static void kwb_msg(const char *fmt, ...)
{
if (verbose_mode) {
va_list ap;
va_start(ap, fmt);
vfprintf(stdout, fmt, ap);
va_end(ap);
}
}
static int openssl_err(const char *msg)
{
unsigned long ssl_err = ERR_get_error();
fprintf(stderr, "%s", msg);
fprintf(stderr, ": %s\n",
ERR_error_string(ssl_err, 0));
return -1;
}
static int kwb_load_rsa_key(const char *keydir, const char *name, RSA **p_rsa)
{
char path[PATH_MAX];
RSA *rsa;
FILE *f;
if (!keydir)
keydir = ".";
snprintf(path, sizeof(path), "%s/%s.key", keydir, name);
f = fopen(path, "r");
if (!f) {
fprintf(stderr, "Couldn't open RSA private key: '%s': %s\n",
path, strerror(errno));
return -ENOENT;
}
rsa = PEM_read_RSAPrivateKey(f, 0, NULL, "");
if (!rsa) {
openssl_err("Failure reading private key");
fclose(f);
return -EPROTO;
}
fclose(f);
*p_rsa = rsa;
return 0;
}
static int kwb_load_cfg_key(struct image_tool_params *params,
unsigned int cfg_option, const char *key_name,
RSA **p_key)
{
struct image_cfg_element *e_key;
RSA *key;
int res;
*p_key = NULL;
e_key = image_find_option(cfg_option);
if (!e_key) {
fprintf(stderr, "%s not configured\n", key_name);
return -ENOENT;
}
res = kwb_load_rsa_key(params->keydir, e_key->key_name, &key);
if (res < 0) {
fprintf(stderr, "Failed to load %s\n", key_name);
return -ENOENT;
}
*p_key = key;
return 0;
}
static int kwb_load_kak(struct image_tool_params *params, RSA **p_kak)
{
return kwb_load_cfg_key(params, IMAGE_CFG_KAK, "KAK", p_kak);
}
static int kwb_load_csk(struct image_tool_params *params, RSA **p_csk)
{
return kwb_load_cfg_key(params, IMAGE_CFG_CSK, "CSK", p_csk);
}
static int kwb_compute_pubkey_hash(struct pubkey_der_v1 *pk,
struct hash_v1 *hash)
{
EVP_MD_CTX *ctx;
unsigned int key_size;
unsigned int hash_size;
int ret = 0;
if (!pk || !hash || pk->key[0] != 0x30 || pk->key[1] != 0x82)
return -EINVAL;
key_size = (pk->key[2] << 8) + pk->key[3] + 4;
ctx = EVP_MD_CTX_create();
if (!ctx)
return openssl_err("EVP context creation failed");
EVP_MD_CTX_init(ctx);
if (!EVP_DigestInit(ctx, EVP_sha256())) {
ret = openssl_err("Digest setup failed");
goto hash_err_ctx;
}
if (!EVP_DigestUpdate(ctx, pk->key, key_size)) {
ret = openssl_err("Hashing data failed");
goto hash_err_ctx;
}
if (!EVP_DigestFinal(ctx, hash->hash, &hash_size)) {
ret = openssl_err("Could not obtain hash");
goto hash_err_ctx;
}
EVP_MD_CTX_cleanup(ctx);
hash_err_ctx:
EVP_MD_CTX_destroy(ctx);
return ret;
}
static int kwb_import_pubkey(RSA **key, struct pubkey_der_v1 *src, char *keyname)
{
RSA *rsa;
const unsigned char *ptr;
if (!key || !src)
goto fail;
ptr = src->key;
rsa = d2i_RSAPublicKey(key, &ptr, sizeof(src->key));
if (!rsa) {
openssl_err("error decoding public key");
goto fail;
}
return 0;
fail:
fprintf(stderr, "Failed to decode %s pubkey\n", keyname);
return -EINVAL;
}
static int kwb_export_pubkey(RSA *key, struct pubkey_der_v1 *dst, FILE *hashf,
char *keyname)
{
int size_exp, size_mod, size_seq;
const BIGNUM *key_e, *key_n;
uint8_t *cur;
char *errmsg = "Failed to encode %s\n";
RSA_get0_key(key, NULL, &key_e, NULL);
RSA_get0_key(key, &key_n, NULL, NULL);
if (!key || !key_e || !key_n || !dst) {
fprintf(stderr, "export pk failed: (%p, %p, %p, %p)",
key, key_e, key_n, dst);
fprintf(stderr, errmsg, keyname);
return -EINVAL;
}
/*
* According to the specs, the key should be PKCS#1 DER encoded.
* But unfortunately the really required encoding seems to be different;
* it violates DER...! (But it still conformes to BER.)
* (Length always in long form w/ 2 byte length code; no leading zero
* when MSB of first byte is set...)
* So we cannot use the encoding func provided by OpenSSL and have to
* do the encoding manually.
*/
size_exp = BN_num_bytes(key_e);
size_mod = BN_num_bytes(key_n);
size_seq = 4 + size_mod + 4 + size_exp;
if (size_mod > 256) {
fprintf(stderr, "export pk failed: wrong mod size: %d\n",
size_mod);
fprintf(stderr, errmsg, keyname);
return -EINVAL;
}
if (4 + size_seq > sizeof(dst->key)) {
fprintf(stderr, "export pk failed: seq too large (%d, %zu)\n",
4 + size_seq, sizeof(dst->key));
fprintf(stderr, errmsg, keyname);
return -ENOBUFS;
}
cur = dst->key;
/* PKCS#1 (RFC3447) RSAPublicKey structure */
*cur++ = 0x30; /* SEQUENCE */
*cur++ = 0x82;
*cur++ = (size_seq >> 8) & 0xFF;
*cur++ = size_seq & 0xFF;
/* Modulus */
*cur++ = 0x02; /* INTEGER */
*cur++ = 0x82;
*cur++ = (size_mod >> 8) & 0xFF;
*cur++ = size_mod & 0xFF;
BN_bn2bin(key_n, cur);
cur += size_mod;
/* Exponent */
*cur++ = 0x02; /* INTEGER */
*cur++ = 0x82;
*cur++ = (size_exp >> 8) & 0xFF;
*cur++ = size_exp & 0xFF;
BN_bn2bin(key_e, cur);
if (hashf) {
struct hash_v1 pk_hash;
int i;
int ret = 0;
ret = kwb_compute_pubkey_hash(dst, &pk_hash);
if (ret < 0) {
fprintf(stderr, errmsg, keyname);
return ret;
}
fprintf(hashf, "SHA256 = ");
for (i = 0 ; i < sizeof(pk_hash.hash); ++i)
fprintf(hashf, "%02X", pk_hash.hash[i]);
fprintf(hashf, "\n");
}
return 0;
}
static int kwb_sign(RSA *key, void *data, int datasz, struct sig_v1 *sig,
char *signame)
{
EVP_PKEY *evp_key;
EVP_MD_CTX *ctx;
unsigned int sig_size;
int size;
int ret = 0;
evp_key = EVP_PKEY_new();
if (!evp_key)
return openssl_err("EVP_PKEY object creation failed");
if (!EVP_PKEY_set1_RSA(evp_key, key)) {
ret = openssl_err("EVP key setup failed");
goto err_key;
}
size = EVP_PKEY_size(evp_key);
if (size > sizeof(sig->sig)) {
fprintf(stderr, "Buffer to small for signature (%d bytes)\n",
size);
ret = -ENOBUFS;
goto err_key;
}
ctx = EVP_MD_CTX_create();
if (!ctx) {
ret = openssl_err("EVP context creation failed");
goto err_key;
}
EVP_MD_CTX_init(ctx);
if (!EVP_SignInit(ctx, EVP_sha256())) {
ret = openssl_err("Signer setup failed");
goto err_ctx;
}
if (!EVP_SignUpdate(ctx, data, datasz)) {
ret = openssl_err("Signing data failed");
goto err_ctx;
}
if (!EVP_SignFinal(ctx, sig->sig, &sig_size, evp_key)) {
ret = openssl_err("Could not obtain signature");
goto err_ctx;
}
EVP_MD_CTX_cleanup(ctx);
EVP_MD_CTX_destroy(ctx);
EVP_PKEY_free(evp_key);
return 0;
err_ctx:
EVP_MD_CTX_destroy(ctx);
err_key:
EVP_PKEY_free(evp_key);
fprintf(stderr, "Failed to create %s signature\n", signame);
return ret;
}
static int kwb_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig,
char *signame)
{
EVP_PKEY *evp_key;
EVP_MD_CTX *ctx;
int size;
int ret = 0;
evp_key = EVP_PKEY_new();
if (!evp_key)
return openssl_err("EVP_PKEY object creation failed");
if (!EVP_PKEY_set1_RSA(evp_key, key)) {
ret = openssl_err("EVP key setup failed");
goto err_key;
}
size = EVP_PKEY_size(evp_key);
if (size > sizeof(sig->sig)) {
fprintf(stderr, "Invalid signature size (%d bytes)\n",
size);
ret = -EINVAL;
goto err_key;
}
ctx = EVP_MD_CTX_create();
if (!ctx) {
ret = openssl_err("EVP context creation failed");
goto err_key;
}
EVP_MD_CTX_init(ctx);
if (!EVP_VerifyInit(ctx, EVP_sha256())) {
ret = openssl_err("Verifier setup failed");
goto err_ctx;
}
if (!EVP_VerifyUpdate(ctx, data, datasz)) {
ret = openssl_err("Hashing data failed");
goto err_ctx;
}
if (EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key) != 1) {
ret = openssl_err("Could not verify signature");
goto err_ctx;
}
EVP_MD_CTX_cleanup(ctx);
EVP_MD_CTX_destroy(ctx);
EVP_PKEY_free(evp_key);
return 0;
err_ctx:
EVP_MD_CTX_destroy(ctx);
err_key:
EVP_PKEY_free(evp_key);
fprintf(stderr, "Failed to verify %s signature\n", signame);
return ret;
}
static int kwb_sign_and_verify(RSA *key, void *data, int datasz,
struct sig_v1 *sig, char *signame)
{
if (kwb_sign(key, data, datasz, sig, signame) < 0)
return -1;
if (kwb_verify(key, data, datasz, sig, signame) < 0)
return -1;
return 0;
}
static int kwb_dump_fuse_cmds_38x(FILE *out, struct secure_hdr_v1 *sec_hdr)
{
struct hash_v1 kak_pub_hash;
struct image_cfg_element *e;
unsigned int fuse_line;
int i, idx;
uint8_t *ptr;
uint32_t val;
int ret = 0;
if (!out || !sec_hdr)
return -EINVAL;
ret = kwb_compute_pubkey_hash(&sec_hdr->kak, &kak_pub_hash);
if (ret < 0)
goto done;
fprintf(out, "# burn KAK pub key hash\n");
ptr = kak_pub_hash.hash;
for (fuse_line = 26; fuse_line <= 30; ++fuse_line) {
fprintf(out, "fuse prog -y %u 0 ", fuse_line);
for (i = 4; i-- > 0;)
fprintf(out, "%02hx", (ushort)ptr[i]);
ptr += 4;
fprintf(out, " 00");
if (fuse_line < 30) {
for (i = 3; i-- > 0;)
fprintf(out, "%02hx", (ushort)ptr[i]);
ptr += 3;
} else {
fprintf(out, "000000");
}
fprintf(out, " 1\n");
}
fprintf(out, "# burn CSK selection\n");
idx = image_get_csk_index();
if (idx < 0 || idx > 15) {
ret = -EINVAL;
goto done;
}
if (idx > 0) {
for (fuse_line = 31; fuse_line < 31 + idx; ++fuse_line)
fprintf(out, "fuse prog -y %u 0 00000001 00000000 1\n",
fuse_line);
} else {
fprintf(out, "# CSK index is 0; no mods needed\n");
}
e = image_find_option(IMAGE_CFG_BOX_ID);
if (e) {
fprintf(out, "# set box ID\n");
fprintf(out, "fuse prog -y 48 0 %08x 00000000 1\n", e->boxid);
}
e = image_find_option(IMAGE_CFG_FLASH_ID);
if (e) {
fprintf(out, "# set flash ID\n");
fprintf(out, "fuse prog -y 47 0 %08x 00000000 1\n", e->flashid);
}
fprintf(out, "# enable secure mode ");
fprintf(out, "(must be the last fuse line written)\n");
val = 1;
e = image_find_option(IMAGE_CFG_SEC_BOOT_DEV);
if (!e) {
fprintf(stderr, "ERROR: secured mode boot device not given\n");
ret = -EINVAL;
goto done;
}
if (e->sec_boot_dev > 0xff) {
fprintf(stderr, "ERROR: secured mode boot device invalid\n");
ret = -EINVAL;
goto done;
}
val |= (e->sec_boot_dev << 8);
fprintf(out, "fuse prog -y 24 0 %08x 0103e0a9 1\n", val);
fprintf(out, "# lock (unused) fuse lines (0-23)s\n");
for (fuse_line = 0; fuse_line < 24; ++fuse_line)
fprintf(out, "fuse prog -y %u 2 1\n", fuse_line);
fprintf(out, "# OK, that's all :-)\n");
done:
return ret;
}
static int kwb_dump_fuse_cmds(struct secure_hdr_v1 *sec_hdr)
{
int ret = 0;
struct image_cfg_element *e;
e = image_find_option(IMAGE_CFG_SEC_FUSE_DUMP);
if (!e)
return 0;
if (!strcmp(e->name, "a38x")) {
FILE *out = fopen("kwb_fuses_a38x.txt", "w+");
if (!out) {
fprintf(stderr, "Couldn't open eFuse settings: '%s': %s\n",
"kwb_fuses_a38x.txt", strerror(errno));
return -ENOENT;
}
kwb_dump_fuse_cmds_38x(out, sec_hdr);
fclose(out);
goto done;
}
ret = -ENOSYS;
done:
return ret;
}
static size_t image_headersz_align(size_t headersz, uint8_t blockid)
{
/*
* Header needs to be 4-byte aligned, which is already ensured by code
* above. Moreover UART images must have header aligned to 128 bytes
* (xmodem block size), NAND images to 256 bytes (ECC calculation),
* and SATA and SDIO images to 512 bytes (storage block size).
* Note that SPI images do not have to have header size aligned
* to 256 bytes because it is possible to read from SPI storage from
* any offset (read offset does not have to be aligned to block size).
*/
if (blockid == IBR_HDR_UART_ID)
return ALIGN(headersz, 128);
else if (blockid == IBR_HDR_NAND_ID)
return ALIGN(headersz, 256);
else if (blockid == IBR_HDR_SATA_ID || blockid == IBR_HDR_SDIO_ID)
return ALIGN(headersz, 512);
else
return headersz;
}
static size_t image_headersz_v0(int *hasext)
{
size_t headersz;
headersz = sizeof(struct main_hdr_v0);
if (image_count_options(IMAGE_CFG_DATA) > 0) {
headersz += sizeof(struct ext_hdr_v0);
if (hasext)
*hasext = 1;
}
return image_headersz_align(headersz, image_get_bootfrom());
}
static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
int payloadsz)
{
struct image_cfg_element *e;
size_t headersz;
struct main_hdr_v0 *main_hdr;
uint8_t *image;
int has_ext = 0;
/*
* Calculate the size of the header and the size of the
* payload
*/
headersz = image_headersz_v0(&has_ext);
image = malloc(headersz);
if (!image) {
fprintf(stderr, "Cannot allocate memory for image\n");
return NULL;
}
memset(image, 0, headersz);
main_hdr = (struct main_hdr_v0 *)image;
/* Fill in the main header */
main_hdr->blocksize =
cpu_to_le32(payloadsz);
main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = has_ext;
main_hdr->version = 0;
main_hdr->destaddr = cpu_to_le32(params->addr);
main_hdr->execaddr = cpu_to_le32(params->ep);
main_hdr->blockid = image_get_bootfrom();
e = image_find_option(IMAGE_CFG_NAND_ECC_MODE);