From d5ab0dce35ae7ccdf07c32dbaae2482c89cf6c9c Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 10 Oct 2024 14:43:26 +0300 Subject: [PATCH] Add base sequence and constrain the reading addresses --- .../flash_seq_lib/flash_async_reset_seq.py | 18 ++------- .../flash_seq_lib/flash_base_seq.py | 39 +++++++++++++++++++ .../flash_seq_lib/flash_rd_wr_seq.py | 20 ++-------- .../flash_seq_lib/flash_read_seq.py | 18 ++------- 4 files changed, 48 insertions(+), 47 deletions(-) create mode 100644 verify/uvm-python/flash_seq_lib/flash_base_seq.py diff --git a/verify/uvm-python/flash_seq_lib/flash_async_reset_seq.py b/verify/uvm-python/flash_seq_lib/flash_async_reset_seq.py index eea0300..c4b26ba 100644 --- a/verify/uvm-python/flash_seq_lib/flash_async_reset_seq.py +++ b/verify/uvm-python/flash_seq_lib/flash_async_reset_seq.py @@ -8,13 +8,12 @@ from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do import random import cocotb +from flash_seq_lib.flash_base_seq import flash_base_seq - -class flash_async_reset_seq(bus_seq_base): +class flash_async_reset_seq(flash_base_seq): def __init__(self, name="flash_async_reset_seq", memory_size=1024): - super().__init__(name) - self.memory_size = memory_size + super().__init__(name, memory_size) async def body(self): # get register names/address conversion dict @@ -22,17 +21,6 @@ async def body(self): # await cocotb.start(self.send_async_reset()) await self.read_rand_addresses() - async def read_bulk(self, address): - bulk_size = random.randrange(3, 50) - for _ in range(bulk_size): - self.create_new_item() - self.req.rand_mode(0) - self.req.addr = address - self.req.kind = bus_item.READ - self.req.data = 0 # needed to add any dummy value - await uvm_do(self, self.req) - address += 4 - async def read_rand_addresses(self): for _ in range(500): address = random.randrange(0, self.memory_size, 4) diff --git a/verify/uvm-python/flash_seq_lib/flash_base_seq.py b/verify/uvm-python/flash_seq_lib/flash_base_seq.py new file mode 100644 index 0000000..ee57cc2 --- /dev/null +++ b/verify/uvm-python/flash_seq_lib/flash_base_seq.py @@ -0,0 +1,39 @@ +from uvm.seq import UVMSequence +from uvm.macros.uvm_object_defines import uvm_object_utils +from uvm.macros.uvm_message_defines import uvm_fatal +from EF_UVM.bus_env.bus_item import bus_item +from uvm.base.uvm_config_db import UVMConfigDb +from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base +from cocotb.triggers import Timer +from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do +import random +import cocotb + + +class flash_base_seq(bus_seq_base): + + def __init__(self, name="flash_async_reset_seq", memory_size=1024): + super().__init__(name) + self.memory_size = memory_size + + async def body(self): + await super().body() + + async def read_bulk(self, address, error=False): + bulk_size = random.randrange(3, 50) + for _ in range(bulk_size): + self.create_new_item() + self.req.rand_mode(0) + self.req.addr = address + if error: + self.req.kind = bus_item.WRITE + else: + self.req.kind = bus_item.READ + self.req.data = 0 # needed to add any dummy value + await uvm_do(self, self.req) + address += 4 + if address >= self.memory_size: + return + + +uvm_object_utils(flash_base_seq) diff --git a/verify/uvm-python/flash_seq_lib/flash_rd_wr_seq.py b/verify/uvm-python/flash_seq_lib/flash_rd_wr_seq.py index 806150a..df7745e 100644 --- a/verify/uvm-python/flash_seq_lib/flash_rd_wr_seq.py +++ b/verify/uvm-python/flash_seq_lib/flash_rd_wr_seq.py @@ -7,12 +7,11 @@ from cocotb.triggers import Timer from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do import random +from flash_seq_lib.flash_base_seq import flash_base_seq - -class flash_rd_wr_seq(bus_seq_base): +class flash_rd_wr_seq(flash_base_seq): def __init__(self, name="flash_rd_wr_seq", memory_size=1024): - super().__init__(name) - self.memory_size = memory_size + super().__init__(name, memory_size) async def body(self): # send write requests as well. it should do nothing but we need to cover the effect @@ -22,19 +21,6 @@ async def body(self): is_error = True if random.random() < 0.2 else False # write 20% of the time await self.read_bulk(address=address, error=is_error) - async def read_bulk(self, address, error=False): - bulk_size = random.randrange(3, 50) - for _ in range(bulk_size): - self.create_new_item() - self.req.rand_mode(0) - self.req.addr = address - if error: - self.req.kind = bus_item.WRITE - else: - self.req.kind = bus_item.READ - self.req.data = 0 # needed to add any dummy value - await uvm_do(self, self.req) - address += 4 uvm_object_utils(flash_rd_wr_seq) diff --git a/verify/uvm-python/flash_seq_lib/flash_read_seq.py b/verify/uvm-python/flash_seq_lib/flash_read_seq.py index 7d83f12..106ea8f 100644 --- a/verify/uvm-python/flash_seq_lib/flash_read_seq.py +++ b/verify/uvm-python/flash_seq_lib/flash_read_seq.py @@ -7,12 +7,11 @@ from cocotb.triggers import Timer from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do import random +from flash_seq_lib.flash_base_seq import flash_base_seq - -class flash_read_seq(bus_seq_base): +class flash_read_seq(flash_base_seq): def __init__(self, name="flash_read_seq", memory_size=1024): - super().__init__(name) - self.memory_size = memory_size + super().__init__(name, memory_size) async def body(self): # get register names/address conversion dict @@ -23,17 +22,6 @@ async def body(self): address = random.randrange(0, self.memory_size, 4) await self.read_bulk(address=address) - async def read_bulk(self, address): - bulk_size = random.randrange(3, 50) - for _ in range(bulk_size): - self.create_new_item() - self.req.rand_mode(0) - self.req.addr = address - self.req.kind = bus_item.READ - self.req.data = 0 # needed to add any dummy value - await uvm_do(self, self.req) - address += 4 - async def read_address(self, address): self.create_new_item() self.req.rand_mode(0)